ABB REG670 - Simplified Logic Schemes

UL1
R1 + j X1
IL1
RFPE
Phase-to-earth
fault in phase L1
Phase-to-phase
fault in phase
L1-L2
Three-phase
fault or Phase-to-
phase-earth fault
(Arc + tower
resistance)
0
(R0-R1)/3 +
j (X0-X1)/3 )
IN
UL1
R1 + j X1
IL1
UL2
R1 + j X1
IL2
RFPP
UL1
R1 + j X1
IL1
UL3
R1 + j X1
IL3
0.5·RFPP
0.5·RFPP
(Arc resistance)
Phase-to-earth
element
Phase-to-phase
element L1-L2
Phase-to-phase
element L1-L3
IEC11000419-2-en.vsd
IEC11000419 V2 EN
Figure 97: Fault loop model
7.4.7.8 Simplified logic schemes
PHSL1, PHSL2,...PHSL3L1 are internal binary logical signals from the Phase-
selection element. They correspond directly to the six loops of the distance zones and
determine which loops should be released to possibly issue a start or a trip.
FWL1, FWL2,...FWL3L1 and RVL1, RVL2,...RVL3L1 are the internal binary
signals from the Directional element. An FW signal is set true if the criteria for a
forward fault or load is fulfilled for its particular loop. The equivalent applies to the
reverse (RV) signals.
The internal input 'IN present' is true if the residual current (3I0) exceeds 7% of IBase.
However, if current transformer saturation is detected, this criterion is changed to
residual voltage (3U0) exceeding 5% of UBase/sqrt(3) instead.
Section 7 1MRK502052-UEN B
Impedance protection
244
Technical manual