ABB REG670 - Page 493

a<b
a
b
U1<
U
TR1
ST1
IEC09000785-3-en.vsd
t
t1
tReset1
R
t
AND
IEC09000785 V3 EN
Figure 229: Detailed logic diagram for step 1, DT operation
U1<
ST1
TR1
tReset1
t1
IEC10000039-3-en.vsd
IEC10000039 V3 EN
Figure 230: Example for Definite Time Delay stage1 reset
1MRK502052-UEN B Section 9
Voltage protection
487
Technical manual