ABB REG670 - Page 507

U1>
U
a>b
a
b
t
tReset1
t
t1
AND
TR1
ST1
OFF
Delay
ON
Delay
IEC10000100-2-en.vsd
IEC10000100 V2 EN
Figure 238: Detailed logic diagram for step 1, definite time delay, DT operation
tReset1
U1>
START
TRIP
t1
IEC10000037-2-en.vsd
IEC10000037 V2 EN
Figure 239: Example for step 1, Definite Time Delay stage 1 reset
1MRK502052-UEN B Section 9
Voltage protection
501
Technical manual