ABB REG670 - Page 519

U1>
U
a>b
a
b
t
tReset1
t
t1
AND
TR1
ST1
OFF
Delay
ON
Delay
IEC10000100-2-en.vsd
IEC10000100 V2 EN
Figure 245: Detailed logic diagram for step 1, Definite time delay, DT operation
U1<
ST1
TR1
tReset1
t1
IEC10000039-3-en.vsd
IEC10000039 V3 EN
Figure 246: Example for Definite Time Delay stage 1 reset
1MRK502052-UEN B Section 9
Voltage protection
513
Technical manual