ABB REG670 - Dead Line Detection

DeltaIL1
DeltaUL1
DeltaIL2
DeltaUL2
DeltaIL3
DeltaUL3
STDIL1
STDIL2
STDIL3
STDI
STDU
STDUL1
STDUL2
STDUL3
IEC12000165-1-en.vsd
intBlock
OROR
20 ms
20 ms
OR
t
20 ms
t
20 ms
t
20 ms
AND
AND
AND
AND
AND
AND
AND
AND
t
20 ms
t
20 ms
t
20 ms
t
20 ms
t
t
IEC12000165 V1 EN
Figure 291: Internal signals DeltaU or DeltaI and the corresponding output
signals
13.2.7.3 Dead line detection
A simplified diagram for the functionality is found in figure 292. A dead phase
condition is indicated if both the voltage and the current in one phase is below their
respective setting values UDLD< and IDLD<. If at least one phase is considered to be
dead the output DLD1PH and the internal signal DeadLineDet1Ph is activated. If all
three phases are considered to be dead the output DLD3PH is activated
1MRK502052-UEN B Section 13
Secondary system supervision
615
Technical manual