ABB REG670 - Logic Diagrams

The internal logic for each function block as well as, the input and outputs, and the
setting parameters with default setting and setting ranges is described in this
document. For application related information, please refer to the application manual.
14.1.7.2 Logic diagrams
Logic diagrams
The logic diagrams that follow illustrate the main principles of the SESRSYN
function components such as Synchrocheck, Synchronizing, Energizing check and
Voltage selection, and are intended to simplify the understanding of the function.
Synchrocheck
The voltage difference, frequency difference and phase angle difference values are
measured in the IED centrally and are available for the synchrocheck function for
evaluation. By setting the phases used for SESRSYN, with the settings SelPhaseBus1,
SelPhaseBus2, SelPhaseLine1 and SelPhaseLine2, a compensation is made
automatically for the voltage amplitude difference and the phase angle difference
caused if different setting values are selected for both sides of the breaker. If needed
an additional phase angle adjustment can be done for selected line voltage with the
PhaseShift setting.
When the function is set to OperationSC = On, the measuring will start.
The function will compare the bus and line voltage values with the set values for
UHighBusSC and UHighLineSC.
If both sides are higher than the set values, the measured values are compared with the
set values for acceptable frequency, phase angle and voltage difference: FreqDiffA,
FreqDiffM, PhaseDiffA, PhaseDiffM and UDiffSC. If additional phase angle
adjustment is done with the PhaseShift setting, the adjustment factor is deducted from
the line voltage before the comparison of the phase angle values.
The frequency on both sides of the circuit breaker is also measured. The frequencies
must not deviate from the rated frequency more than +/-5Hz. The frequency
difference between the bus frequency and the line frequency is measured and may not
exceed the set value FreqDiff.
Two sets of settings for frequency difference and phase angle difference are available
and used for the manual closing and autoreclose functions respectively, as required.
The inputs BLOCK and BLKSC are available for total block of the complete
SESRSYN function and selective block of the Synchrocheck function respectively.
Input TSTSC will allow testing of the function where the fulfilled conditions are
connected to a separate test output.
The outputs MANSYOK and AUTOSYOK are activated when the actual measured
conditions match the set conditions for the respective output. The output signal can be
delayed independently for MANSYOK and AUTOSYOK conditions.
Section 14 1MRK502052-UEN B
Control
632
Technical manual