ABB REG670 - Logic Diagram

14.2.6.4 Logic diagram
QB_OP
QB_CL
S1QC1_CL
en04000544.vsd
=1
=1
=1
VPQB VPDCTR
DCOPTR
DCCLTR
S1QC1_OP
S2QC2_OP
S2QC2_CL
VPS1QC1
VPS2QC2
&
>1
&
&
1
QBOPITL
QBOPREL
VPS1QC1
VPS2QC2
VPS1_DC
S1QC1_OP
S2QC2_OP
S1DC_OP
EXDU_ES
EXDU_BB
QBOP_EX1
VPS1QC1
VPS2QC2
VPS2_DC
S1QC1_OP
S2QC2_OP
S2DC_OP
EXDU_ES
EXDU_BB
QBOP_EX2
VPS1QC1
VPS2QC2
S1QC1_CL
S2QC2_CL
EXDU_ES
QBOP_EX3
A1A2_DC
IEC04000544 V1 EN
IEC04000545 V1 EN
14.2.6.5 Signals
Table 375: A1A2_DC Input signals
Name
Type Default Description
QB_OP BOOLEAN 0 QB is in open position
QB_CL BOOLEAN 0 QB is in closed position
S1QC1_OP BOOLEAN 0 QC1 on bus section 1 is in open position
S1QC1_CL BOOLEAN 0 QC1 on bus section 1 is in closed position
Table continues on next page
1MRK502052-UEN B Section 14
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