8. Inject the faulty phase voltage in accordance with the test point P1.
9. At this condition, the outputs ZIN and ZOUT get deactivated and START signal will be maintained
for a set duration of tH.
10. To detect consecutive power swings, repeat steps 5, 6, 7 and 8. With this condition, the output
START will be activated.
11. Repeat step 6 and inject before the expiration of timer tW. The output ZOUT will be activated.
12. Repeat step 7 after a set duration of tP2. The output ZIN will be activated.
13. At this condition, it will be detected as consecutive power swing and the output signal START will
be maintained.
14. Repeat step
8 and the outputs ZOUT and ZIN get deactivated. The output signal START will
disappear after set duration of tH from the instance of step
13.
15. Repeat the above steps to test and detect power swing condition in at least two phases by enabling
input REL2PH.
16. By enabling the input BLK1PH, operation mode for power swing detection in any phase will be
blocked.
17. Similarly, operation mode for power swing detection in at least two phases will be blocked by
enabling the input BLK2PH.
18. Repeat steps
5, 6 and 7, and enable the input signal BLOCK. At this condition, the outputs START,
ZOUT and ZIN will be deactivated.
19. Output signal START will also get activated instantaneously by enabling input EXTERNAL and this
input signal can be configured in ACT to the output derived from some external logics used to
detect power swings. By enabling the input signal BLOCK, the output signal START will be
deactivated.
Testing the inhibit logic of power swing detection function
GUID-1E0D044A-89F5-4382-B78E-0927E271C54E v1
The following output signals shall be configured to binary output available: ZOUT, measured impedance
within outer impedance boundary and ZIN, measured impedance within inner impedance boundary and
START, power swing detection.
1. Set X1InFw, R1LIn, X1InRv, R1FInFw, R1FInRv, ArgLd, RLdOutFw, RLdOutRv, kLdRFw and
kLdRRv to values that are in accordance with the selectivity plan and the corresponding operating
characteristic is shown in Figure
40.
2. Set OperationLdCh to On and set timers tP1, tP2, tW, tH, tR1, tR2 and tEF to their default values.
3. Enable the input signal REL1PH to detect the power swing in one of the three phases.
Inhibit START output by the presence of residual current
GUID-B1AFF8D6-FD37-47AA-84A4-DD98E920CCA7 v1
Preconditions
The input signal I0CHECK, residual current (3I0) detection used to inhibit the start output, must be
configured to the output signal STPE on the FDPSPDIS, FRPSPDIS, ZMFPDIS or ZMFCPDIS function.
The input signal BLKI02, block inhibit of the start output for subsequent residual current detection, is
connected to FALSE.
1. Create a test sequence such that power swing has been detected, which can be done by referring
to steps 5, 6 and 7 described in section
Testing the power swing detection logic ZMBURPSB and
1MRK 504 165-UUS Rev. J Section 11
Testing functionality by secondary injection
Transformer protection RET670 137
Commissioning manual
© 2017 - 2021 Hitachi Power Grids. All rights reserved
To Next Page
Loading...
