ABB Relion 670 series - Page 1003

15.14.6 Operation principle
GUID-62FB35B1-488D-4927-B050-E3967ADFF670 v3
In the pulse integrator TIGAPC, the time during which the input is high is integrated. This means
there is no output until the sum of the input pulses equals the set time delay to operate. The
output is deactivated when the input signal is FALSE and the time delay to reset has elapsed.
Integration
0
0
0
t
t
t
1
t
Reset
In
t
int
t
Delay
Out
IEC13000175-2-en.vsd
IEC13000175 V2 EN-US
Figure 519: IN pulse length sufficient for integration to reach the set t
Delay
, OUT is set until
the t
Reset
time has elapsed, which resets t
Delay
and OUT
0
0
0
t
t
t
In
Integration
1
t
int
t
Delay
t
Reset
Out
IEC13000174=2=en.vsd
IEC13000174 V1 EN-US
Figure 520: IN pulse too short for integration to reach the set t
Delay
0
0
0
t
t
t
1
In
Integration
t
int
t
Delay
Out
t
Reset
t
Reset
t
Reset
IEC13000176-2-en.vsd
IEC13000176 V1 EN-US
Figure 521: IN pulse too short for integration to reach the set t
Delay
, and t
Reset
resets
integration before next pulse can be integrated.
1MRK 502 066-UUS B Section 15
Logic
997
Technical manual