0
0
0
t
t
t
1
In
Integration
t
int
t
Delay
Out
t
Reset
t
Reset
t
Reset
IEC13000177-2-en.vsd
IEC13000177 V2 EN-US
Figure 522: The next IN pulse is received before t
Reset
has elapsed. Sufficient time during the
pulses is accumulated to reach t
Delay
. When t
Delay
is reached, OUT is set until t
Reset
time has elapsed, which resets t
Delay
and OUT.
t
int
integration time
t
Reset
time delay to reset
t
Delay
time delay to operate
GUID-44D82B7D-280F-4F11-B017-784E3047AD0F v3
Table 705: TIGAPC technical data
Function Cycle time (ms) Range of value Accuracy
Time integration
continuous active 3 0-999999.99 s
±0.2% or ±20 ms whichever is
greater
Time integration
continuous active
8 0-999999.99 s ± 0.2% or ±50 ms whichever is
greater
Time integration
continuous active
100 0-999999.99 s ±0.2% or ±250 ms whichever is
greater
Table 706: Number of TIGAPC instances
Function Quantity with cycle time
3 ms 8 ms 100 ms
TIGAPC - 30 -
15.15 Elapsed time integrator with limit transgression and
overflow supervision TEIGAPC
15.15.1 Identification
GUID-1913E066-37D1-4689-9178-5B3C8B029815 v2
Function Description
IEC 61850
identification
IEC 60617
identification
ANSI/IEEE C37.2 device
number
Elapsed time integrator TEIGAPC - -
Section 15 1MRK 502 066-UUS B
Logic
998
Technical manual
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