respectively. Note that by setting
tResetn
=
0.0s
, instantaneous reset of the definite time delayed
stage is ensured.
a<b
a
b
Pickup1
V
TRST1
PU_ST1
AND
0
t1
tReset1
0
R
ANSI09000785-3-en.vsd
ANSI09000785 V3 EN-US
Figure 326: Logic diagram for step 1, DT operation
Pickup1
PU_ST1
TRST1
tReset1
t1
ANSI10000039-3-en.vsd
ANSI10000039 V3 EN-US
Figure 327: Example for Definite Time Delay stage1 reset
Section 9 1MRK 502 066-UUS B
Voltage protection
608
Technical manual
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