ABB RELION REX640 - 9.1.9.2 Technical revision history; 9.1.9.3 Technical revision history

9.1.9.1 Technical revision history
Table 1471: CBXCBR Technical revision history
Product
connectivi
ty level
Technical
revision
Change
PCL4 G
Input SYN_ITL_BYPS is devided into two inputs SYN_BYPASS
and ITL_BYPASS. New output CTL_ITL_BLKD and pulse timer
setting Interlocking Pls Len added.
9.1.9.2 Technical revision history
Table 1472: DCXSWI Technical revision history
Product
connectivi
ty level
Technical
revision
Change
PCL4 E
New output CTL_ITL_BLKD and pulse timer setting Interlocking
Pls Len added.
9.1.9.3 Technical revision history
Table 1473: ESXSWI Technical revision history
Product
connectivi
ty level
Technical
revision
Change
PCL4 E
New output CTL_ITL_BLKD and pulse timer setting Interlocking
Pls Len added.
1MRS759142 F Control functions
REX640
Technical Manual
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