Acer AR380 F2 - Technical Specifications; PCIe Specifications

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Acer AR380 F2 specifications
Technical specifications
PCIe
®
specifications
The primary I/O bus for the main board is PCIe
®
Gen3. The following table lists the characteristics of the
PCI-E bus segments. Details about each bus segment follow the table.
NOTE: The signaling bit rate of PCI Express is 8.0Gbit/s one direction per lane for Gen 3
Expansion
slot
Number
CPU
Type
Bus
width
1
Voltage
Connector
Location
Length
PCIe x16
1
2
PCIe
Gen3
X16
3.3V
X16
Left riser
Full height
Full length
PCIe x8
1
1
PCIe
Gen3
X8
3.3V
X8
Left riser
Full height
Full length
PCIe x16
1
1
PCIe
Gen3
x16
3.3V
x16
Left riser
Full height
Full length
PCIe x8
1
1
PCIe
Gen3
X8
3.3V
X8
Left riser
Full height
Half length
PCIe x8
1
2
PCIe
Gen3
X8
3.3V
X8
Right riser
Low profile
Half length
PCIe x8
1
2
PCIe
Gen3
X8
3.3V
X8
Right riser
Low profile
Half length
NOTE:
1. Indicates the number of physical electrical lanes running to a PCIe
®
connector.
2. CPU 2 indicates that a second CPU is required to access that specific PCIe
®
slot.
3. Default bus assignment (in decimal). Inserting cards with PCI™ bridges may alter the actual bus
assignment number.
4. Slots are enumerated differently based on the operating system. Microsoft® operating systems
enumerate Device ID by bus starting from the lowest bus to the highest.