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P-State Coordination In HW_ALL mode, the processor hardware is
responsible for coordinating the P-state among logical
processors dependencies. The OS is responsible for
keeping the P-state request up to date on all logical
processors.
In SW_ALL mode, the OS Power Manager is
responsible for coordinating the P-state among logical
processors with dependencies and must initiate the
transition on all of those Logical Processors.
In SW_ANY mode, the OS Power Manager is
responsible for coordinating the P-state among logical
processors with dependencies and may initiate the
transition on any of those Logical Processors.
HW_ALL
SW_ALL
SW_ANY
C1E Support Select whether to enable the C1 Enhanced mode for the
processor. If enabled, all logical processors in a physical
processor will run in a C1 state.
Enabled
Disabled
CPU C3 Report Enable/Disable C3 Report. Enabled
Disabled
CPU C6 Report Enable/Disable C6 Report. Enabled
Disabled
Package C State Limit Configure state for the C-State package limit. C0
C1
C6
C7
No Limit
Hardware Prefetcher Select whether to enable the speculative prefetch unit o
djacent Cache Line
Prefetch
When enabled, cache lines are fetched in pairs. When
disabled, only the required cache line is fetched.
Enabled
Disabled
CPU Speed The processor speed is the speed at which a
microprocessor executes instructions. Clock speeds are
expressed in megahertz (MHz), with
1 MHz being equal to 1 million cycles per second. The
faster the clock, the more instructions the CPU can
execute per second.
EMT64 Display Processor EMT64 support status
Core Count Display Processor core count information.
CPU Stepping Display processor stepping information.
Microcode Revision Display Microcode Revision.
Intel HT Technology Display Intel Hyper Threading Technology function
support information.
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