Akai RC-90 - Page 5

V. SCHEMATIC DIAGRAM OF ICs
MS0110P
KEY INPUT
ENCODER
KEY IN
TIMING
GENERATOR
SCAN SIGNAL
GENERATOR
2)—@)
osc
osc OUT
IN ouT TRANSMISSION
OUTPUT
TRANSMISSION CODE (MS5OIIOP
CODE
ii —» "9"
| | —» "|"
EXAMPLE
MUU LULL,
000 1 ! 000 0 i ; :
1 WORD (10 BIT)
25ms
WAVE FORM OF LSi MS5OIIOP PIN @ (RC-90T/RC-9IT)
ewo HMMM DAMM _,,
MLL AA
LILA NAA _,, 8
re UL I A
LULL,
LULA
LULL, A
LULA,
REV
STOP
REW
AUTO MUTE
(RC-90T: REC MUTE)
REC PAUSE
.(RC-90T > REC)
AUTO FADER
(RC-90T ; PAUSE)
M50111P
wen Se
OSC OUT
— ___| AUTO CLEAR
AC mO CIRCUIT
ey RECEPTION
Si ((4)—mO] SIGNAL INPUT | |
CIRCUIT
KLOCK
INPUT
FOR SD/CL
SERIAL DATA
SHIFT REGISTOR
Mae iNT (12) PROCESSOR
OUTPUT
TC40H002P
INSTRUCTION
DECODER
E MULTIPLE
KEY JUDGE
(16) Vpp (2.2 to BV)
(1) Vss (Ov)
PIN ©)
TC4028BP
Voo
BCD TO DECIMAL
ao
uJ
Q
Oo
S)
ve
Q
Vss
(16) Vpp (4.5 to BV)
TIMING
GENERATOR
(1) Vgg (ov)
ae, SurRuE |
a CIRCUIT ee a
(4) D9
DEMODULATOR ©) | ara
| | bp | OUTPUT
me Tt”
MALFUNCTION
PREVENTION
CIRCUIT a
STA DECODE
(9) sted ouTPUT
RECEPTION a
DETECTION n RECEPTION
CIRCUIT IR| INDICATE
OUTPUT
SERIAL-DATA
(10) so laucrur
4A 4yY 3B 3A 3Y
TRUTH TABLE
INPUTS SELECTED
po fe | eta tH
pe tetetetl a |
pete tetay a
Petey atecl e |
pete yet ay] os
peta pete
pete fet Hw | os |
pe tH [Hie] oe |
petuiwxtH |] oe
pHi *® | ete] oe
pH {etal Hy] a9 |
%&: DON'T CARE
Vec
LIMITER |
LEVEL -
WAVEFORM
SHAPPER
| PEAK
DETECTOR