Allen-Bradley Ultra1500 2092-DA1 - Velocity Regulator

Publication 2092-UM001D-EN-P — July 2005
Ultra1500 Application Examples 5-41
Velocity Regulator
Figure 5.21 shows the block diagram of the velocity regulator in the Ultra1500:
Figure 5.21
Velocity Regulator Block Diagram
The Ultra1500 uses a fixed frequency (5 kHz) to sample data and perform
computations (i.e., the sample or update rate is 200 µs). A z
-1
block in the
figure indicates a delay of one update period, or 200 µs. This implies that any
signal multiplied by a z
-1
block will use the signal from the previous update in
the calculation for the current update.
Block/Switch definitions shown in Figure 5.21 refer to the Ultraware parameter names where applicable.
K
d
1/K
p
0.0
z
-1
+
+
+
+
+
6
3
I
bias
5
Integral
Term
-
z
-1
z
-1
z
-1
z
-1
+
+
+
-
Integrator
Anti-windup
+
+
7 8
Derivative
Term
+
+
9 10 11
1
+
-
Sampled
Velocity
Command
Current
Command
Sampled
Velocity
Feedback
K
p
2
K
i
4
Block/Switch Definitions:
1 Main Drive Window : Velocity Limits : Velocity Limit Mode & Manual Velocity Limit
2 Tuning Window : Main Velocity Regulator Gains : P.
3 Tuning Window : Main Velocity Regulator Gains : Integrator Mode.
4 Tuning Window : Main Velocity Regulator Gains : Integral Time. Ki is the inverse of the Integral Time
5 Main Drive Window : Initial Current Bias
6 The integral term is set to the initial current bias when the drive is disabled.
7 A 30 Hz low pass filter is applied to the derivative of the error. The user cannot change this parameter setting
8 Tuning Window : Main Velocity Regulator Gains : D.
9 Main Drive Window : Current Limits; Main Drive Window : Stopping Functions : Maximum Stopping Current
10 Tuning Window : Main Current Regulator Gains : Low Pass Filter Bandwidth
11 Tuning Window : Main Current Regulator Gains : Resonant Frequency Suppression
Velocity
Cmd
Limit
Current
Cmd
Limit
Current
Cmd
Low Pass
Filter
Current
Cmd
Notch Filter