System Control Coprocessor
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3.2.33 c11, DMA identification and status registers
The purpose of the DMA identification and status registers is to define:
• the DMA channels that are physically implemented on the particular device
• the current status of the DMA channels.
Processes that handle DMA can read this register to determine the physical resources
implemented and their availability.
The DMA Identification and Status Register is:
• in CP15 c11
• four 32-bit read-only registers common to Secure and Non-secure worlds
• accessible only in privileged modes.
Figure 3-59 shows the format of DMA identification and status registers 0-3.
Figure 3-59 DMA identification and status registers format
Table 3-104 lists how the bit values correspond with the DMA identification and status registers.
Table 3-105 lists the Opcode_2 values used to select the DMA channel function.
C
H
0
UNP
31 210
C
H
1
Table 3-104 DMA identification and status register bit functions
Bits Field name Function
[31:2] - UNP/SBZ
[1] CH1 Provides information on DMA Channel 1 functions:
0 = DMA Channel 1 function
a
disabled
1 = DMA Channel 1 function
a
enabled.
a. See Table 3-105 for the function of the channel that Opcode_2 of the MRC
instruction determines.
[0] CH0 Provides information on DMA Channel 0 functions:
0 = DMA Channel 0 function
a
disabled
1 = DMA Channel 0 function
a
enabled.
Table 3-105 DMA Identification and Status Register functions
Opcode_2 Function
0 Indicates channel present:
0 = the channel is not Present
1 = the channel is Present.
1 Indicates channel queued:
0 = the channel is not Queued
1 = the channel is Queued.
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