ARM ARM1176JZF-S - Table 6-15 Access Types from Second-Level Descriptor Bit Values; Generating a Second-Level Page Table Address

Memory Management Unit
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6.12.3 Second-level page table walk
If bits [1:0] of the first-level descriptor bits are b01, then a page table walk is required. The
MMU requests the second-level page table descriptor from external memory. Figure 6-13 shows
how the second-level page table address is generated.
Figure 6-13 Generating a second-level page table address
When the page table address is generated, a request is made to external memory for the
second-level descriptor.
By examining bits [1:0] of the second-level descriptor, the access type is indicated as Table 6-15
lists.
Second-level translation fault
If bits [1:0] of the second-level descriptor are b00, then a translation fault is generated. This
generates an abort to the processor, either a Prefetch Abort for the instruction side or a Data
Abort for the data side, see MMU fault checking on page 6-29.
N
S
1
Coarse page table base address
31 10 9 8 5 4 2 1 0
P Domain 0
First-level table index
31 20 19 12 11 0
Second-level
table index
Translation base
31 14 13 0
0
Coarse page table base address
31 10 9 2 1 0
Second-level
table index
0
0
Translation base
31 14 13 0
First-level table index 0
21
Second-level descriptor address
First-level descriptor
First-level descriptor address
Modified virtual address
Translation table base
3
SBZ SBZ
Table 6-15 Access types from second-level descriptor bit values
Descriptor format Bit values Access type
Both b00 Translation fault
Backwards-compatible b01 64KB large page
ARMv6 b01 64KB large page
Backwards- compatible b10 4KB small page
ARMv6 b1XN 4KB extended small page
Backwards- compatible b11 4KB extended small page