VFP Programmer’s Model
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20.4.4 Instruction registers, FPINST and FPINST2
The VFP11 coprocessor has two instruction registers:
• The FPINST register contains the exceptional instruction.
• The FPINST2 register contains the instruction that was issued to the VFP11 coprocessor
before the exception was detected. This instruction was retired in the ARM11 processor
and cannot be reissued. It must be executed by support code.
The FPINST and FPINST2 are accessible only in privileged modes.
The instruction in the FPINST register is in the same format as the issued instruction but is
modified in several ways. The condition code flags, FPINST[31:28], are forced to b1110, the
AL, always, condition. If the instruction is a short vector, the source and destination registers
that reference vectors are updated to point to the source and destination registers of the
exceptional iteration. See Exception processing for CDP short vector instructions on page 22-8
for more information.
The instruction in the FPINST2 register is in the same format as the issued instruction but is
modified by forcing the condition code flags, FPINST2[31:28] to b1110, the AL, always,
condition.
[10:8] VECITR Vector iteration count field.
VECITR contains the number of remaining short vector iterations after a potential exception was
detected in one of the iterations:
b000 = 1 iteration
b001 = 2 iterations
b010 = 3 iterations
b011 = 4 iterations
b100 = 5 iterations
b101 = 6 iterations
b110 = 7 iterations
b111 = 0 iterations.
[7] INV Input exception flag.
Set if the VFP11 coprocessor is not in flush-to-zero mode and an operand is subnormal or if the
VFP11 coprocessor is not in default NaN mode and an operand is a NaN.
[6:4] - Should Be Zero.
[3] UFC Potential underflow flag.
Set if the VFP11 coprocessor is not in flush-to-zero mode and a potential underflow condition
exists.
[2] OFC Potential overflow flag.
Set if the OFE bit, FPSCR[10], is set, the VFP11 coprocessor is not in RunFast mode, and a
potential overflow condition exists.
[1] - Should Be Zero.
[0] IOC Potential invalid operation flag.
Set if the IOE bit, FPSCR[8], is set, the VFP11 coprocessor is not in RunFast mode, and a potential
invalid operation condition exists.
Table 20-8 Encoding of the Floating-Point Exception Register (continued)
Bits Name Description
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