ARM ARM1176JZF-S - Global Signals; Table A-1 Global Signals

Signal Descriptions
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A.1 Global signals
Table A-1 lists the processor global signals.
Free clocks are the free running clocks with minimal insertion delay for clocking the clock
gating circuitry. Free clocks must be balanced with the incoming clock signal, but not with the
clocks clocking the core logic.
Table A-1 Global signals
Name Direction Description
CLKIN Input Core clock
FREECLKIN Input Free running version of the core clock
nPORESETIN Input Power on reset, resets debug logic
nRESETIN Input Core reset, not for VFP
nVFPRESETIN Input VFP reset
STANDBYWFI Output Indicates that the processor is in Standby mode
VFPCLAMP Input Controls clamping logic between core and VFP
RAMCLAMP Input Enables the clamp cells in Dormant mode
CPUCLAMP Input Enables the clamp cells between VDD Core and VDD SoC
ACLKENP Input Clock enable for the peripheral port to enable it to be clocked at a reduced rate
ACLKEND Input Clock enable for the DMA port to enable it to be clocked at a reduced rate
ACLKENI Input Clock enable for the instruction port to enable it to be clocked at a reduced rate
ACLKENRW Input Clock enable for the data port to enable it to be clocked at a reduced rate
ARESETIn Input AXI reset for Instruction IEM Register Slice
ARESETRWn Input AXI reset for Data IEM Register Slice
ARESETPn Input AXI reset for Peripheral IEM Register Slice
ARESETDn Input AXI reset for DMA IEM Register Slice
ACLKI Input AXI clock for Instruction IEM Register Slice
ACLKRW Input AXI clock for Data IEM Register Slice
ACLKP Input AXI clock for Peripheral IEM Register Slice
ACLKD Input AXI clock for DMA IEM Register Slice
SYNCMODEREQI Input Request for synchronous or asynchronous mode of Instruction IEM Register
Slice
SYNCMODEREQRW Input Request for synchronous or asynchronous mode of Data IEM Register Slice
SYNCMODEREQP Input Request for synchronous or asynchronous mode of Peripheral IEM Register
Slice
SYNCMODEREQD Input Request for synchronous or asynchronous mode of DMA IEM Register Slice
SYNCMODEACKI Output Acknowledge for synchronous or asynchronous mode of Instruction IEM
Register Slice