Signal Descriptions
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-11
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• the read data bus is implemented as RDATAD[63:0]
• the ARSIDEBANDD[4:0] output and AWSIDEBANDD[4:0] output signals are
implemented to indicate shared and inner cacheable accesses
• the WRITEBACK output signal is implemented to indicate cache line evictions.
The DMA port is a 64-bit wide AXI port that is read/write. Table A-9 lists the DMA port signals.
Table A-9 DMA port signals
Name Direction Type Description
AWLEND[3:0] Output Write Write burst length:
b0000, 1 data transfer
b0001, 2 data transfers
b0010, 3 data transfers
b0011, 4 data transfers, maximum for the DMA port.
AWSIZED[2:0] Output Write Write burst size:
b000, indicating 8-bit transfer
b001, indicating 16-bit transfer
b010, indicating 32-bit transfer
b011, indicating 64-bit transfer.
AWBURSTD[1:0] Output Write Write burst type:
b00, FIXED, fixed burst
b01, INCR, incrementing burst.
AWLOCKD[1:0] Output Write Write lock type, always set to b00, indicating normal access.
ARLEND[3:0] Output Read Burst length that gives the exact number of transfer:
b0000, 1 data transfer
b0011, 4 data transfers.
ARSIZED[2:0] Output Read Burst size:
b000, indicating 8-bit transfer
b001, indicating 16-bit transfer
b010, indicating 32-bit transfer
b011, indicating 64-bit transfer.
ARBURSTD[1:0] Output Read Burst type:
b00, FIXED, fixed burst
b01, INCR, incrementing burst.
ARLOCKD[1:0] Output Read Lock type, always set to b00, indicating normal access.
ARSIDEBANDD[4:0] Output Read Indicates read accesses to shared and inner cacheable memory.
AWSIDEBANDD[4:0] Output Write Indicates write accesses to shared and inner cacheable memory.
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