Glossary
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Arithmetic instruction
Any VFPv2 Coprocessor Data Processing (CDP) instruction except FCPY, FABS, and FNEG.
See also CDP instruction.
ARM instruction A word that specifies an operation for an ARM processor to perform. ARM instructions must
be word-aligned.
ARM state A processor that is executing ARM (32-bit) word-aligned instructions is operating in ARM
state.
ASIC See Application Specific Integrated Circuit.
ASSP See Application Specific Standard Part/Product.
ATB See Advanced Trace Bus.
ATB bridge A synchronous ATB bridge provides a register slice to facilitate timing closure through the
addition of a pipeline stage. It also provides a unidirectional link between two synchronous ATB
domains.
An asynchronous ATB bridge provides a unidirectional link between two ATB domains with
asynchronous clocks. It is intended to support connection of components with ATB ports
residing in different clock domains.
ATPG See Automatic Test Pattern Generation.
Automatic Test Pattern Generation (ATPG)
The process of automatically generating manufacturing test vectors for an ASIC design, using
a specialized software tool.
AXI See Advanced eXtensible Interface.
AXI channel order and interfaces
The block diagram shows:
• the order in which AXI channel signals are described
• the master and slave interface conventions for AXI components.
AXI terminology The following AXI terms are general. They apply to both masters and slaves:
Active read transaction
A transaction for which the read address has transferred, but the last read data has
not yet transferred.
Active transfer
A transfer for which the xVALID
1
handshake has asserted, but for which
xREADY has not yet asserted.
Active write transaction
A transaction for which the write address or leading write data has transferred, but
the write response has not yet transferred.
AXI
interconnect
Write address channel (AW)
Write data channel (W)
Write response channel (B)
Read address channel (AR)
Read data channel (R)
Write address channel (AW)
Write data channel (W)
Write response channel (B)
Read address channel (AR)
Read data channel (R)
AXI slave
interface
AXI master
interface
AXI
master
AXI
slave
AXI master
interface
AXI slave
interface
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