ARM ARM7TDMI - Reset Sequence After Power Up

Open Access
A-20
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.19 Test Interface Controller and Connecters
Date: February 26, 1996 Sheet
Size Document Number
B ARM EOI-0011B (TIC.
Title
Test Interface Controller a
n
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
1OEAB
1
1LEAB
2
1CEAB
3
GND
4
1A0
5
1A1
6
VCC
7
1A2
8
1A3
9
1A4
10
GND
11
1A5
12
1A6
13
1A7
14
2A0
15
2A1
16
2A2
17
GND
18
2A3
19
2A4
20
2A5
21
VCC
22
2A6
23
2A7
24
GND
25
2CEAB
26
2LEAB
27
2OEAB
28
2OEBA
29
2LEBA
30
2CEBA
31
GND
32
2B7
33
2B6
34
VCC
35
2B5
36
2B4
37
2B3
38
GND
39
2B2
40
2B1
41
2B0
42
1B7
43
1B6
44
1B5
45
GND
46
1B4
47
1B3
48
1B2
49
VCC
50
1B1
51
1B0
52
GND
53
1CEBA
54
1LEBA
55
1OEBA
56
U40
FCT16543
GND
GND
GND
VCC
B_D16
B_D17
B_D18
B_D19
B_D20
B_D21
B_D22
B_D23
B_D24
B_D25
B_D26
B_D27
nTICEN
nT_DEN
GND
1OEAB
1
1LEAB
2
1CEAB
3
GND
4
1A0
5
1A1
6
VCC
7
1A2
8
1A3
9
1A4
10
GND
11
1A5
12
1A6
13
1A7
14
2A0
15
2A1
16
2A2
17
GND
18
2A3
19
2A4
20
2A5
21
VCC
22
2A6
23
2A7
24
GND
25
2CEAB
26
2LEAB
27
2OEAB
28
2OEBA
29
2LEBA
30
2CEBA
31
GND
32
2B7
33
2B6
34
VCC
35
2B5
36
2B4
37
2B3
38
GND
39
2B2
40
2B1
41
2B0
42
1B7
43
1B6
44
1B5
45
GND
46
1B4
47
1B3
48
1B2
49
VCC
50
1B1
51
1B0
52
GND
53
1CEBA
54
1LEBA
55
1OEBA
56
U41
FCT16543
GND
GND
GND
VCC
GND
GND
GND
VCC
GND
GND
GND
VCC
T_D0
T_D1
T_D2
T_D3
T_D4
T_D5
T_D6
T_D7
T_D8
T_D9
T_D10
T_D11
T_D16
T_D17
T_D18
T_D19
T_D20
T_D21
T_D22
T_D23
T_D24
T_D25
T_D26
T_D27
B_D0
B_D1
B_D2
B_D3
B_D4
B_D5
B_D6
B_D7
B_D8
B_D9
B_D10
B_D11
nB_DEN
nB_DLEN
nTICEN
nB_DEN
nB_DLEN
nTICEN
nT_DEN
GND
nTICEN
1OEAB
1
1LEAB
2
1CEAB
3
GND
4
1A0
5
1A1
6
VCC
7
1A2
8
1A3
9
1A4
10
GND
11
1A5
12
1A6
13
1A7
14
2A0
15
2A1
16
2A2
17
GND
18
2A3
19
2A4
20
2A5
21
VCC
22
2A6
23
2A7
24
GND
25
2CEAB
26
2LEAB
27
2OEAB
28
2OEBA
29
2LEBA
30
2CEBA
31
GND
32
2B7
33
2B6
34
VCC
35
2B5
36
2B4
37
2B3
38
GND
39
2B2
40
2B1
41
2B0
42
1B7
43
1B6
44
1B5
45
GND
46
1B4
47
1B3
48
1B2
49
VCC
50
1B1
51
1B0
52
GND
53
1CEBA
54
1LEBA
55
1OEBA
56
U38
FCT16543
R181
10K
GND
GND
GND
VCC
GND
GND
GND
VCC
T_D16
T_D17
T_D18
T_D19
T_D20
T_D21
T_D22
T_D23
T_D24
T_D25
T_D26
T_D27
B_A16
B_A17
B_A18
B_A19
B_A20
B_A21
B_A22
B_A23
B_A24
B_A25
B_A26
B_A27
nB_AEN
nB_ALEN
nTICEN
VCC VCC
1OEAB
1
1LEAB
2
1CEAB
3
GND
4
1A0
5
1A1
6
VCC
7
1A2
8
1A3
9
1A4
10
GND
11
1A5
12
1A6
13
1A7
14
2A0
15
2A1
16
2A2
17
GND
18
2A3
19
2A4
20
2A5
21
VCC
22
2A6
23
2A7
24
GND
25
2CEAB
26
2LEAB
27
2OEAB
28
2OEBA
29
2LEBA
30
2CEBA
31
GND
32
2B7
33
2B6
34
VCC
35
2B5
36
2B4
37
2B3
38
GND
39
2B2
40
2B1
41
2B0
42
1B7
43
1B6
44
1B5
45
GND
46
1B4
47
1B3
48
1B2
49
VCC
50
1B1
51
1B0
52
GND
53
1CEBA
54
1LEBA
55
1OEBA
56
U39
FCT16543
R180
10K
GND
GND
GND
VCC
GND
GND
GND
VCC
T_D0
T_D1
T_D2
T_D3
T_D4
T_D5
T_D6
T_D7
T_D8
T_D9
T_D10
T_D11
B_A0
B_A1
B_A2
B_A3
B_A4
B_A5
B_A6
B_A7
B_A8
B_A9
B_A10
B_A11
nB_AEN
nB_ALEN
nTICEN
ADDRESS TRANSCEIVERS
R183
10K
A_GNTTIC
nB_CLK9
B_CLK9
B_RES[1..0]
VCC
GND
VCC
GND
T_D12
T_D13
T_D14
T_D15
B_A12
B_A13
B_A14
B_A15
nTICEN
nB_ALEN
nB_AEN
A_GNTTIC
B_CLK9
nB_CLK9
B_RES[1..0]
TEST INTERFACE CONTROLLER
R182
10K
1
V168
1
V170
1
V169
1
V171
VCC
GND
VCC
GND
T_D28
T_D29
T_D30
T_D31
B_A28
B_A29
B_A30
B_A31
nTICEN
nB_ALEN
nB_AEN
VCCVCC
DATA TRANSCEIVERS
VCC
GND
VCC
GND
VCC
GND
T_D12
T_D13
T_D14
T_D15
T_D28
T_D29
T_D30
T_D31
B_D12
B_D13
B_D14
B_D15
nTICEN
nB_DLEN
nB_DEN
nTICEN
nB_DLEN
nB_DEN
nTICEN
nT_DEN
GND
TEST INTERFACE HEADE
R
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
TEST1
CON20AP
VCC
VCC
GND
B_D28
B_D29
B_D30
B_D31
nTICEN
nT_DEN
GND
T_CLK
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
TEST2
CON20AP
GND
GND
VCC
T_D0
T_D1T_D2
T_D3T_D4
T_D5T_D6
T_D7T_D8
T_D9T_D10
T_D1T_D12
T_D1T_D14
T_D1
T_D16
T_D1T_D18
T_D1T_D20
T_D2T_D22
T_D2T_D24
T_D2T_D26
T_D2T_D28
T_D2T_D30
T_D3
T_REQA
T_REQB
T_ACK
ENABLE TRANSCEIVERS
SPARE I/O
nTICEN IS DRIVEN LOW TO
INSERT LINK TO USE TIC
1
V167
R179
10K
1
V175
VCC
MONITOR POINTS
IO5
7
IO6
8
IO7
9
I0
10
I1
11
GND
12
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
I
O
1
2
1
8
I
O
1
3
1
9
I
O
1
4
2
0
I
O
1
5
2
1
V
C
C
2
2
G
N
D
2
3
I
O
1
6
2
4
I
O
1
7
2
5
I
O
1
8
2
6
I
O
1
9
2
7
I
O
2
0
2
8
IO21
29
IO22
30
IO23
31
I3
32
I4
33
GND
34
CLK1/I5
35
IO24
36
IO25
37
IO26
38
IO27
39
I
O
2
8
4
0
I
O
2
9
4
1
I
O
3
0
4
2
I
O
3
1
4
3
V
C
C
4
4
G
N
D
1
I
O
0
2
I
O
1
3
I
O
2
4
I
O
3
5
I
O
4
6
U37
MACH210A-7
1
V172
1
V173
1
V174
A
D
D
R
V
G
R
A
N
T
E
D
B_ERROR
B_LAST
B_WAIT
T_REQA
T_REQB
GND
T_ACK B_RES0
GND
W
R
I
T
E
R
E
A
D
V
C
C
G
N
DQ
0
Q
1
Q
2
A
_
R
E
Q
T
I
C
A
_
G
N
T
T
I
C
nTICEN
B_CLK9
nB_CLK9
B_RES1
T_CLACK
nUSETIC
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_PROT[1..0]
B_LOCK
B_WAIT
A_REQTIC
B_LAST
B_ERROR
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_PROT[1..0]
B_LOCK
B_WAIT
A_REQTIC
B_ERROR
B_LAST
MONITOR POINT
1
V176
C124
10u
C125
100n
C126
100n
C127
100n
C128
100n
C129
100n
C130
100n
V
C
C
G
N
D
B
_
W
R
I
T
E
B
_
P
R
O
T
0
B
_
P
R
O
T
1
B
_
S
I
Z
E
0
B
_
S
I
Z
E
1
B_LOCK
B_TRAN0
B_TRAN1
n
B
_
D
L
E
N
n
T
_
D
E
N
n
B
_
A
E
N
n
B
_
A
L
E
N
nB_DEN
TESTMODE
T_CLK
VCC
GND
VCC
GND
OUT = TIC disabled (default)
IN = TIC enabled
R194
10K
1
2
LK17
LINK
nUSETIC
VCC
GND
DO NOT CONNECT LOGIC A
N
TO THESE HEADERS
h
rg.
b
oo
k
P
age
20
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM