ARM ARM7TDMI - About Coprocessors

Open Access
A-22
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.21 System Modules (Arbiter and Decoder)
Date: February 26, 1996 Sheet
Size Document Number
B EOI-0011B (SYSMODS.
Title
System Modules
CB1 4JN
CAMBRIDGE
CHERRY HINTON
FULBOURN ROAD
(C) ADVANCED RISC MAC
G
N
D
V
C
C
A
_
G
N
T
T
I
C
A
_
G
N
T
A
R
M
A
_
G
N
T
0
0
1
A
_
G
N
T
0
0
2
B
_
E
R
R
O
R
nJTRST
ARBITER AND RESET CONTROLLER
IO5
7
IO6
8
IO7
9
I0
10
I1
11
GND
12
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
I
O
1
2
1
8
I
O
1
3
1
9
I
O
1
4
2
0
I
O
1
5
2
1
V
C
C
2
2
G
N
D
2
3
I
O
1
6
2
4
I
O
1
7
2
5
I
O
1
8
2
6
I
O
1
9
2
7
I
O
2
0
2
8
IO21
29
IO22
30
IO23
31
I3
32
I4
33
GND
34
CLK1/I5
35
IO24
36
IO25
37
IO26
38
IO27
39
I
O
2
8
4
0
I
O
2
9
4
1
I
O
3
0
4
2
I
O
3
1
4
3
V
C
C
4
4
G
N
D
1
I
O
0
2
I
O
1
3
I
O
2
4
I
O
3
5
I
O
4
6
U54
MACH210A-7
EXTPOR
A
_
R
E
Q
T
I
C
A
_
R
E
Q
A
R
M
A
R
E
Q
1
A
R
E
Q
2
GND
Default B-C Default B-C
TIE REQUEST LOW, MOVE IF USED
A
1
C
2
B
3
LK14
SMLINK
A
1
C
2
B
3
LK15
SMLINK
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
D_SELASB0
D_SELASB1
A_REQ001
AREQ1
A_REQ002
AREQ2
GND
B_A[31..2]
B_TRAN[1..0]
B_WAIT
B_LAST
B_ERROR
nB_CLK[8..7]
nENASB[1..0]
B_LOCK
B_TRAN[1..0]
B_WAIT
B_LAST
B_ERROR
B_A[31..2] D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
D_SELASB0
D_SELASB1nB_CLK[8..7]
nENASB[1..0]
B_LOCK
DECODER
REMAP
STANDBY
A_REQTIC
A_REQARM
A_REQ001
A_REQ002
nSYSRST
B_CLK5
B_CLK7
B_RES[2..0]
REMAP
STANDBY
A_REQTIC
A_REQARM
A_REQ001
A_REQ002
A_GNTTIC
A_GNTARM
A_GNT001
A_GNT002
nSYSRST NISARST
B_CLK5
nJTRST
B_CLK7
A_GNTTIC
A_GNTARM
A_GNT001
A_GNT002
B_RES[2..0]
NISARST
nJTRST
VCC
REMAP
1
2
LK18
LINK
R210
10K
OUT - always remapped
IN - remap enabled (default)
REMAPPED
GND
B
_
A
7
B
_
A
8
B
_
A
9
B
_
A
1
0
B_A11
B_A12
BOUNDARY
STANDBY
nB_CLK8
nSYSRST
D_SELASB0
B_WAIT
B_LAST
GND
V
C
C
G
N
D
B_RES0
B_RES1
B_RES2
B
_
A
2
B
_
A
3
B
_
A
4
B
_
A
5
B
_
A
6
D_SELASB1
nENASB0
nENASB1
B_CLK7
B_LOCK
NISARST
RESET MONITOR POINT
1
V207
1
V208
EXTPOR
nEXTPOR
D22
1N4148
R196
100K
C109
4u7
11
10
U24E
74HCT14
13
12
U24F
74HCT14
SPARE GATE
VCC
THESE SERIES RESISTORS
ARE AN ATTEMPT TO DAMP
REFLECTIONS AND INCREASE
OVERALL SYSTEM SPEED
SW2
SW PUSHBUTTON
RED CAP
R200
33R
R201
33R
B_A15
B_A16
B_A17
B_A18
GND
nB_CLK7
D_SELASB0
D_SELASB1
SELASB0
SELASB1
IO5
7
IO6
8
IO7
9
I0
10
I1
11
GND
12
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
I
O
1
2
1
8
I
O
1
3
1
9
I
O
1
4
2
0
I
O
1
5
2
1
V
C
C
2
2
G
N
D
2
3
I
O
1
6
2
4
I
O
1
7
2
5
I
O
1
8
2
6
I
O
1
9
2
7
I
O
2
0
2
8
IO21
29
IO22
30
IO23
31
I3
32
I4
33
GND
34
CLK1/I5
35
IO24
36
IO25
37
IO26
38
IO27
39
I
O
2
8
4
0
I
O
2
9
4
1
I
O
3
0
4
2
I
O
3
1
4
3
V
C
C
4
4
G
N
D
1
I
O
0
2
I
O
1
3
I
O
2
4
I
O
3
5
I
O
4
6
U55
MACH210A-7
D
_
S
E
L
A
P
B
D
_
S
E
L
D
R
A
M
D
_
S
E
L
S
R
A
M
G
N
D
V
C
C
B
_
A
1
3
B
_
A
1
4
GND
B_TRAN0
B_TRAN1
D_SELROM
D_SELSSRAM
D_SELNISA
S
E
L
A
S
B
1
S
E
L
A
S
B
0
W
A
I
T
L
A
S
T
B
O
U
N
D
A
R
Y
B
_
A
2
2
B
_
A
2
3
B
_
A
2
4
B
_
A
2
5
B
_
A
2
6
B
_
A
2
7
B
_
A
2
8
B_A29
B_A30
B_A31
V
C
C
G
N
D
B_CLK5
E
R
R
O
R
REMAPPED
C104
10u
R202
33R
R203
33R
R204
33R
B_A19
B_A20
B_A21
B_RES0
B_RES1
B_WAIT
B_LAST
B_ERROR
WAIT
LAST
ERROR
DECOUPLING CAPACITORS
C105
100n
C106
100n
C107
100n
C108
100n
VCC
GND
GND
VCC
GND
h
rg.
b
oo
k
P
age
22
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM