ARM ARM7TDMI - Coprocessor Interface Handshaking

Open Access
B-3
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Daughter Board Schematics
B.2 Top-level Diagram
Date: June 14, 1996 Sheet
Size Document Number
B ARM EOI-0016B (CHAMPQ
F
Title
ARM7T Development Board He
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
LOGIC ANALYSER PODS BLOCK
LAPODS.SCH
nIRQ
A[31..0]
MCLK
D[31..0]
nFIQ
SIZE[1..0]
PROT[1..0]
WRITE
LOCK
PIPEF
nEXEC
nMREQ
SEQ
RES1
nCPI
ABORT
nM[4..0]
DBGACK
TBIT
ECLK
CPA
CPB
TRAN[1..0]
nPWAIT
A[31..0]
D[31..0]
WRITE
SIZE[1..0]
PROT[1..0]
LOCK
MCLK
nFIQ
nIRQ
PIPEF
RES[1..0]
WAIT
MCLK
LAST
ERROR
BIGEND
ISYNC
RES1
nPWAIT
HEADER CARD CONNECTOR BLOCK
HDRCONN.SCH
TRAN[1..0]
A[31..0]
WRITE
SIZE[1..0]
PROT[1..0]
LOCK
RES[1..0]
MCLK
WAIT
LAST
ERROR
nFIQ
nIRQ
BIGEND
ISYNC
REQARM
nCPI
COMMTX
COMMRX
CPA
CPB
GNTARM
EXTERN[1..0]
nICERST
D[31..0]
nTRST
nMABE
A[31..0]
D[31..0]
WRITE
SIZE[1..0]
TRAN[1..0]
PROT[1..0]
LOCK
SEQ
nMREQ
A[31..0]
D[31..0]
WRITE
SIZE[1..0]
TRAN[1..0]
PROT[1..0]
LOCK
nICERST
PROCESSOR BLOCK
PROCQFP.SCH
D[31..0]
A[31..0]
WRITE
SIZE[1..0]
PROT[1..0]
LOCK
nMREQ
SEQ
nM[4..0]
nEXEC
TBIT
DBGACK
ECLK
COMMTX
COMMRX
TDOTDI
TMS
TCK
nTRST
MCLK
WAIT
nWAIT
WSEL
MTBE
MDBE
BIGEND
ISYNC
nFIQ
nIRQ
ABORT
RES1
TMUX[1..0]
CPA
CPB
EXTERN[1..0]
nCPI
BMEN[1..0]
TRAN[1..0]
MTBE
MDBE
WSEL
WAIT
MCLK
nWAIT
ABORT
RES1
TDI
TCK
TMS
nTRST
BIGEND
ISYNC
nFIQ
nIRQ
TMUX[1..0]
AMBA VENEER BLOCK
AMBAPLD.SCH
MCLK
MTBE
MDBEWAIT
WSEL
nWAIT
PIPEF
ABORT
TMUX[1..0]
REQARM
BMEN[1..0]
SEQ
nMREQ
LOCK
WRITE
PROT[1..0]
RES[1..0]
LAST
ERROR
GNTARM
TRAN[1..0]
nMABE
nPWAIT
TDO
nM[4..0]
nEXEC
TBIT
ECLK
DBGACK
COMMRX
COMMTX
COMMRX
COMMTX
nCPI
REQARM
nMABE
nM[4..0]
DBGACK
ABORT
nFIQ
nIRQ
nEXEC
nTRST
EXTERN[1..0]
CPB
CPA
GNTARM
TBIT
ECLK
nMREQ
SEQ
nCPI
CPA
EMBEDDED ICE CONNECTOR
EICE.SCH
TDO
TDI
TMS
TCK
nICERST
TDI
TCK
TMS
nIC
E
MTBE
MDBE
WSEL
nWAIT
ABORT
PIPEF
TDO
TMUX[1..0]
CPB
TRAN[1..0]
nMABE
nPWAIT
CAPACITORS
WRITE
MCLK
WAIT
LOCK
nMREQ
SEQ
nCPI
RES[1..0]
ERROR
LAST
PROT[1..0]
5V DECOUPLING
C1
10u
C2
100n
C3
100n
EXTERN[1..0]
CPB
CPA
BMEN[1..0]
VCC
3V3 DECOUPLING
VCC is system 5V
VDD is system 3V3
VSS is system ground
BOARD OUTLINE
DRAWING.SCH
C6
10u
C7
100n
C8
100n
C9
100n
C10
100n
VDD
VSS
VSS
CAPACITORS
GNTARM
GROUND TEST PINS
TRAN[1..0]
REQARM
BMEN[1..0]
1
TP1
TESTPIN
1
TP2
TESTPIN
1
TP3
TEST
P
VSS VSS VSS
h
rg.
b
oo
k
P
age
3
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM