ARM ARM7TDMI - B.3 Header Connecters

Open Access
B-4
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Daughter Board Schematics
B.3 Header Connecters
Date: June 14, 1996 Sheet
Size Document Number
B ARM EOI-0016B (CPUHEA
Title
Processor and header co
n
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
VSS
COMMTX
TRAN0
C
O
T
R
W
A
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
21
+
23
+
25
+
27
+
29
+
31
+
33
+
35
+
37
+
39
+
41
+
43
+
45
+
47
+
49
+
51
+
53
+
55
+
57
+
59
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
+
22
+
24
+
26
+
28
+
30
+
32
+
34
+
36
+
38
+
40
+
42
+
44
+
46
+
48
+
50
+
52
+
54
+
56
+
58
+
60
SK4
CON60APS
K
CAPACITORS
3V3 DECOUPLING
VDD
VSS
C17
100n
FOR BUFFERS
D0
D2
D3
VSS
VSS
REQARM
GNTARM
REQ001
GNT001
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
21
+
23
+
25
+
27
+
29
+
31
+
33
+
35
+
37
+
39
+
41
+
43
+
45
+
47
+
49
+
51
+
53
+
55
+
57
+
59
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
+
22
+
24
+
26
+
28
+
30
+
32
+
34
+
36
+
38
+
40
+
42
+
44
+
46
+
48
+
50
+
52
+
54
+
56
+
58
+
60
SK3
CON60APSKT
C12
10u
C13
100n
C14
100n
C15
100n
C16
100n
VSS
VSS
D1
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
21
+
23
+
25
+
27
+
29
+
31
+
33
+
35
+
37
+
39
+
41
+
43
+
45
+
47
+
49
+
51
+
53
+
55
+
57
+
59
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
+
22
+
24
+
26
+
28
+
30
+
32
+
34
+
36
+
38
+
40
+
42
+
44
+
46
+
48
+
50
+
52
+
54
+
56
+
58
+
60
SK1
CON60APSKT
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
21
+
23
+
25
+
27
+
29
+
31
+
33
+
35
+
37
+
39
+
41
+
43
+
45
+
47
+
49
+
51
+
53
+
55
+
57
+
59
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
+
22
+
24
+
26
+
28
+
30
+
32
+
34
+
36
+
38
+
40
+
42
+
44
+
46
+
48
+
50
+
52
+
54
+
56
+
58
+
60
SK2
CON60APSKT
B_A0
B_A2
B_A3
B_A5
B_A6
B_A8
B_A9
A[31..0]
TRAN[1..0]
TRAN[1..0]
A[31..0]
VSS
VSS
B_A1
B_A4
B_A7
COMMRX
COMMTX
D[31..0]
WRITE
SIZE[1..0]
PROT[1..0]
LOCK
WRITE
SIZE[1..0]
PROT[1..0]
LOCK
COMMTX
COMMRX
VSS
VSS
VSS
VSS
VSS
nCPI
D[31..0]
nCPI
REQARM
REQARM
nICERST
nICERST
B_A10
B_A13
B_A16
B_A19
B_A22
B_A25
B_A28
B_A31
B_PROT0
B_SIZE1
VDD
VSS
D10
VSS
D13
D16
VSS
D19
D22
VSS
D25
VSS
D4
D7
D28
D31
B_A11
B_A12
B_A14
B_A15
B_A17
B_A18
B_A20
B_A21
B_A23
B_A24
B_A26
B_A27
B_A29
B_A30
B_PROT1
B_SIZE0
B_WRITE
B_LOCK
D11
D12
D15
D17
D18
D20
D21
D23
D24
VDD
D5
D6
D8
D9
D14
D26
D27
D29
D30
VDD
VSS
EXTERN1
VSS
EXTERN0
TCK
TDO
TMS
TDI
nTRST VSS
C
P
V
D
CPA
VSS
VSS
nCPI
ERROR
MCLK
ISYNC
nIRQ
n
F
B
I
V
S
V
C
R
E
R
E
R
E
n
I
L
A
VSS
VDDVSS
B_A24
B_A25
B_A26
B_A27
B_A28
B_A29
B_A30
B_A31
A24
A25
A26
A27
A28
A29
A30
A31
DIR
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U8
LVT245T
nMA
B
VDD
VSS
VDDVSS
A8
A9
A10
A11
A12
A13
A14
A15
B_A16
B_A17
B_A18
B_A19
B_A20
B_A21
B_A22
B_A23
A16
A17
A18
A19
A20
A21
A22
A23
DIR
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U7
LVT245T
nMABE nMABE
A0
A1
A2
A3
A4
A5
A6
A7VSS
VDDVSS
DIR
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U5
LVT245T
VSS
VSS
B_A0
B_A1
B_A2
B_A3
B_A4
B_A5
B_A6
B_A7
B_A8
B_A9
B_A10
B_A11
B_A12
B_A13
B_A14
B_A15
DIR
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U6
LVT245T
nMABEWAIT
MCLK
ERROR
nFIQ
nIRQ
MCLK
WAIT
ERROR
nFIQ
nIRQ
RES[1..0]
RES[1..0]
LAST
LAST
nMABE
nMABE
ISYNC
BIGEND
CPA
CPB
CPB
CPA
BIGEND
ISYNC
GNTARM
GNTARM
EXTERN[1..0]
EXTERN[1..0]
nTRST
nTRST
DIRECTION IS B->A SO DIR IS LOW
OUTPUT ENABLED BY nMABE
BUFFERS ON ADDRESS AND CONTROL LINES
VSS
VSS
B_SIZE0
B_SIZE1
B_PROT0
B_PROT1
B_WRITE
B_LOCK
DIR
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
GND
10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
U9
LVT245T
VDD
nMABE
SIZE0
SIZE1
PROT0
PROT1
WRITE
LOCK
VSS
VSS
R34
560R
DO NOT FIT
R35
220R
DO NOT FIT
VDD
VSS
WAIT
OPTIONAL TERMINATION RESISTORS
h
rg.
b
oo
k
P
age
4
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM