ARM ARM7TDMI - B.4 Logic Analyser Connecters

Open Access
B-5
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Daughter Board Schematics
B.4 Logic Analyser Connecters
Date: June 14, 1996 Sheet
Size Document Number
B ARM EOI-0016B (LAPOD
S
Title
Logic Analyser connec
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
VDD
(nOPC)
LOGIC ANALYSER PODS
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
POD5
CON20AP
1
V72
VDD
MCLK
nM1PIPEF
nEXEC
VDD
nM0 PROT0
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
POD1
CON20AP
1
V64
1
V65
D14
D12
D15
D13
D11
VDD
A[31..0]
A[31..0]
D[31..0]
D[31..0]
MCLK
TRAN[1..0]
WRITE
SIZE[1..0]
PROT[1..0]
LOCK
PIPEF
nEXEC
WRITE
SIZE[1..0]
TRAN[1..0]
PROT[1..0]
LOCK
MCLK
PIPEF
nEXEC
nMREQ
SEQ
nMREQ
SEQ
nPWAIT
nPWAIT
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
POD2
CON20AP
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
POD3
CON20AP
1
V66
1
V67
D30
D28
D26
D24
D22
D20
D18
D16
D31
D29
D27
D25
D23
D21
D19
D17
VSS
VDD
D10
D8
D6
D4
D2
D0
D9
D7
D5
D3
D1
VSS
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
POD6
CON20AP
1
V76
VSS
TRAN1
SIZE1
PROT1
WRITE
LOCK
SIZE0
TRAN0
nIRQ nFIQ
DBGACK
VSS
VDD
ECLK
RES1
nM2
nM3nM4
VSS
VDD
VSS
SEQ
ABORTnMREQ
(MAS1)
(nRW)
(nRESET)
TBIT
nCPI
CPA CPB
1
V78
1
V77
nPWAIT
1
V84
1
V85
1
V86
VSS
VDD
VSS
(MAS0)
NOTE: PIN 1 OF ALL
5V ON ANALYSER
PODS CONNECTS TO
VDD
VSS
VDD
VSS
+
1
+
3
+
5
+
7
+
9
+
11
+
13
+
15
+
17
+
19
+
2
+
4
+
6
+
8
+
10
+
12
+
14
+
16
+
18
+
20
POD4
CON20AP
1
V68
1
V69
1
V70
1
V71
A15
A13
A11
A9
A7
A5
A3
A1
A14
A12
A10
A8
A6
A4
A2
A0 VSS
VDD
A16
A17A18
A19A20
A21A22
A23A24
A25A26
A27A28
A29A30
A31
VSS
VDD
nFIQ
ABORT
DBGACK
nM[4..0]
nIRQ
TBIT
ECLK
RES1
nFIQ
ABORT
nIRQ
nM[4..0]
DBGACK
TBIT
ECLK
RES1
nCPI
nCPI
CPA
CPB
CPA
CPB
h
rg.
b
oo
k
P
age
5
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM