ARM ARM7TDMI - About the ARM7 TDMI Core

Open Access
Circuit Descriptions
3-5
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.2 Crystal Oscillator and Clock Distribution
This schematic is shown in A.4 Crystal Oscillator and Clock Distribution on page A-5.
A standard 14.318MHz crystal oscillator (X1) is connected to a phase-locked loop (PLL)
based clock-generation device (U5), which generates all the system clocks. These are:
SYSCLK distributed to system
SYSCLK2X double rate system clock
CLK32MHZ 32MHz clock for NISA bus (primary)
CLK24MHZ 24MHz clock for NISA bus (alternative to CLK32MHZ)
COMMCLK 1.843MHz for serial port UART
System clocks
The system clocks, either on-board or external, are distributed to the rest of the board via
three low-skew clock buffer devices (U3,U4 and U6). Each clock output is serially terminated
and drives one load only.
If other system clock frequencies are needed (up to a maximum of 25MHz), an external
source can be applied in place of the SYSCLK and SYSCLK2X outputs from (U5). Both
must be provided and they must be phase-aligned.
External clocks
The external clocks, EXTSCLK and EXTSCLK2X, should be connected to plugs (PL1 and
PL2). Optional 47R resistors can be fitted (R36 and R37) to terminate the clock inputs if
required. To select external clocks instead of the on-board clocks, you have to move the
surface mount links (LK2 and LK3) to the B-C position.
Double-rate clock
The double-rate clock SYSCLK2X is used by the synchronous SRAM to allow single cycle
memory accesses. This is a departure from the AMBA bus methodology, but used in order
to simulate fast “on-chip” memory.
Serial port (UART)
The 1.843MHz COMMCLK drives the serial port (UART) baud rate generator directly.
In addition, this clock is divided down by the PAL (U2) to provide a refresh signal (REFCLK)
at 64kHz for the DRAM controller.
NISA bus devices
The NISACLK is used to drive the NISA bus devices. This is a 32MHz clock signal, derived
from CLK32MHZ, selected by a surface mount link (LK1). The CLK24MHZ output from (U5)
is not normally used.
hrg.book Page 5 Wednesday, July 22, 1998 9:18 AM