Open Access
Circuit Descriptions
3-7
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.3 ASB Slaves
This schematic is shown in
A.5 ASB Slaves
on page A-6, and shows the following ASB
slaves and associated circuitry:
• DRAM controller
• Synchronous SRAM controller
• SRAM controller
• EPROM/FLASH controller
• Memory address and data buffers
• APB and NISA bus bridge
Each memory controller is described in the appropriate section. The memory address and
data buffers are shared by the these controllers as follows:
• B_D is driven onto M_D when nOEMD is driven LOW
• M_D is driven onto B_D when nOEBD is driven LOW
The SRAM controller and the DRAM controller both drive nOEMD and nOEBD, which are
implemented as open-collector active low signals.
M_A is generated by sampling B_A on the falling edge of B_CLK, and is used by the SRAM
and EPROM slaves.
Address and data latches for the APB and NISA buses are implemented separately (see
3.2.15 APB Buffers
on page 3-22).
Link (LK4) is used to select the endianism of the board. The default (link out) is little-endian.
If the link is inserted the BIGEND signal goes high and this is used by the SRAM,
synchronous SRAM and DRAM controllers to enable big-endian style writes. There is no
support for EPROMs that have been programmed big-endian. The BIGEND signal is also
routed to the ARM processor.
hrg.book Page 7 Wednesday, July 22, 1998 9:18 AM
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