Open Access
Circuit Descriptions
3-8
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.4 “On-Chip” Memory (Synchronous SRAM)
The “on-chip” memory (synchronous SRAM) schematic is shown in
A.6 “On-chip” Memory
(Synchronous SRAM)
on page A-7.
A typical AMBA system might comprise some fast “on-chip” memory and various memory
controllers for SRAM, DRAM and EPROM. On the board, a synchronous SRAM device has
been used to simulate “on-chip” memory. By running the device with a double-rate clock,
single-cycle memory access can be achieved.
The controller is implemented as an ASB slave in a fast PAL (U8). The memory device is a
32K x 32-bit pipelined synchronous SRAM capable of being clocked at up to 66MHz.
Because it is a pipelined device, the data is available to be read two clock cycles after the
address is latched. In an ARM system, the data needs to be available in the clock cycle
following the address. Therefore, by running the device at twice the system clock frequency,
the data is read out in the correct system cycle.
Figure 3-1: ASB Sync SRAM Timing Diagram
shows the clock relationship and control
signals.
Figure 3-1: ASB Sync SRAM Timing Diagram
READ DECODE1 WRITE DECODE2 READ MULTIPLE
HOLD READ IDLE IDLE HOLD WRITE IDLE IDLE HOLD READIDLE IDLE HOLD READ READHOLD
0ns 50ns 100ns 150ns 200ns 250ns 300ns 350n
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