Open Access
Circuit Descriptions
3-24
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.19 System Modules (Arbiter and Decoder)
This schematic is shown in
A.21 System Modules (Arbiter and Decoder)
on page A-22.
The schematic shows the two ASB system modules:
• the arbiter
• the decoder
Arbiter
The arbiter (U54) is responsible for deciding which bus master gains control of the ASB.
In addition, this device also controls the system reset B_RES[2:0] lines.
Two surface mount links (LK14 and LK15) are provided to enable the expansion bus request
lines (A_REQ001 and A_REQ002). In normal operation these lines are tied LOW through
the links, but if you connect a bus master to the ASB, you need to enable one or other of
these request lines by moving the appropriate link to the A-C position.
Pressing SW2 (the switch with a red cap) causes a full system reset.
Decoder
The decoder (U55) is responsible for driving the ASB select lines (D_SELxxx) and is vital to
the correct operation of the board. This device can be reprogrammed to implement
alternative memory maps if required.
The decoder functions in two distinct states:
•normal
• reset
On power-up, the board is by default in the reset configuration. In this state the EPROM or
FLASH can be found at the bottom of the address map. If the remap register is written to,
the REMAP signal goes HIGH and the decoder switches to the normal memory map where
there is SRAM at the bottom.
If you are bringing up a system where there is no EPROM or FLASH, you may want to
disable this feature. Link (LK18) is provided for this purpose. In the default position (in),
the REMAP input to the decoder is driven by the REMAP and pause controller implemented
in the APB FPGA. If this link is removed, the REMAP signal is always high, and the board
starts up with SRAM at the bottom of the address map.
Ref Name Description Options Default
LK18 REMAP driven or always high out=high, in=driven in
Table 3-15: LK18
hrg.book Page 24 Wednesday, July 22, 1998 9:18 AM
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