Open Access
Circuit Descriptions
3-26
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.3 ARM7TDMI Processor Daughter Board
This schematic is shown in
B.2 Top-level Diagram
on page B-3.
This AMBA bus master daughter card comprises an ARM7TDMI test chip and a PLD that
converts it into an AMBA master. It is connected to the main board through four 60-way
connectors and provides headers to which a logic analyser may be connected. The JTAG
interface on the test chip is brought out to a header to which an EmbeddedICE interface may
be connected.
The top-level schematic shows the following blocks:
• processor (QPF or PGA)
• header card connectors
• AMBA bus master veneer
• logic analyser connectors
• EmbeddedICE interface connector
3.3.1 Processor in QFP package
This schematic is shown in
B.6 Processor in QFP Package
on page B-7.
This schematic shows the ARM7TDMI test chip in a QFP package. A number of inputs are
tied to default values through resistors.
To learn more about the ARM7TDMI refer to the documents:
•
ARM7TDMI Data Sheet
(ARM DDI 0029) and
•
ARM7TDMI Test Chip Appendix
(ARM DXI 0022).
3.3.2 Processor in PGA package
This schematic is shown in
B.7 Processor in PGA Package
on page B-8.
This schematic shows the ARM7TDMI test chip in a PGA package. It is identical in all other
respects to the QFP packaged device.
3.3.3 Header card connectors
This schematic is shown in
B.3 Header Connecters
on page B-4.
This schematic shows four 60-way connectors (SK1–4) which are used to attach the
daughter card to the main board. A number of the connector pins are not used, these are
reserved for future expansion.
Refer to section
3.2.18 Master Header Connectors and Level Convertors
to see which
ASB signals the processor is connected to.
hrg.book Page 26 Wednesday, July 22, 1998 9:18 AM
To Next Page
Loading...
