Open Access
Circuit Descriptions
3-27
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.3.4 AMBA bus master veneer
This schematic is shown in
B.5 AMBA Bus Master Veneer
on page B-6.
In order to turn an ARM processor (such as the ARM7TDMI test chip) into an AMBA bus
master an AMBA veneer is required. This function is performed by the MACH215 device
(U2). Because this is a 5V part it is necessary to level shift the outputs so that output high
voltages do not damage the processor. The two level convertors (U3 and U4) are
constructed from “Quickswitch” buffers. These devices have very low propagation delay
(less than 250ps) and appear as a 5 ohm resistor when switched on. The output voltage for
an input voltage equal to the supply is approximately 1V below the supply. A resistor/diode
network (R32 and D1) is used to provide a supply of 4.3V, so that high input levels are
clamped to 3.3V when driven out of the device.
There are four surface mount links (LK1–4) which operate as follows. BMEN0 (LK1) and
BMEN1 (LK2) are configuration inputs to the processor and AMBA veneer device. These
links should always be connected A–C as their functionality is reserved for future use.
OLDTC (LK3) allows older revisions of the ARM7TDMI test chip to be used in this system.
Before revision 1 of the ARM7TDMI test chip some of the AMBA signals were not available.
This link configures the AMBA veneer to provide these functions on behalf of the processor.
By default this link is in the B–C position as all production headers will be fitted with revision
1 or higher ARM7TDMI devices.
The GRANT SELECT link (LK4) is used to configure the way in which the processor is
granted and enabled onto ASB. By default this link is in position A–C and should not be
moved.
3.3.5 Logic analyser connectors
This schematic is shown in
B.4 Logic Analyser Connecters
on page B-5.
Six 20-way box headers (POD1–6) are provided to allow connection of Hewlett Packard 20
pin (HP 01650-63203) pods suitable for use with HP1650B-series logic analysers. These
connectors can also be used for expansion purposes. Using a logic analyser it is possible to
observe the processor cycles and if required disassemble ARM instruction mnemonics to
trace program execution. This procedure and the POD pin assignments are covered in detail
in
Chapter 7, The Logic Analyser Interface
.
3.3.6 EmbeddedICE interface
This schematic is shown in
B.8 EmbeddedICE Interface
on page B-9.
This schematic shows the EmbeddedICE JTAG connector (PL1). It is a 14-way box header,
compatible with the ARM EmbeddedICE interface. To connect this device to an
EmbeddedICE unit you will need a short 14-way IDC cable which is supplied with that
interface.
For further information on the EmbeddedICE interface refer to
Chapter 6, The
EmbeddedICE Interface
.
hrg.book Page 27 Wednesday, July 22, 1998 9:18 AM
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