ARM ARM7TDMI - About the Programmers Model

Open Access
Expanding and Monitoring the ASB
4-4
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
4.1.2 List of signals
The following list describes each signal.
Signal Description
B_CLK AMBA system clock
nB_CLK AMBA system clock inverted
B_RES[2:0] AMBA reset signals
B_D[31:0] ASB data bus
B_A[31:0] ASB address bus
B_WAIT ASB wait response
B_LAST ASB last response
B_ERROR ASB error response
B_LOCK ASB locked transfers
B_PROT[1:0] ASB protection control
B_TRAN[1:0] ASB transfer type
B_SIZE[1:0] ASB transfer size
B_WRITE ASB transfer direction
D_SELASB[1:0] ASB expansion select signals
D_SELSSRAM ASB select SSRAM controller
D_SELSRAM ASB select SRAM controller
D_SELDRAM ASB select DRAM controller
D_SELROM ASB select EPROM/FLASH controller
D_SELAPB ASB select APB bridge
D_SELNISA ASB select NISA bridge
nINTASB[1:0] interrupt sources, active low, level sensitive
nFIQSRC fast interrupt source, active low, level sensitive
Table 4-1: ASB signals
hrg.book Page 4 Wednesday, July 22, 1998 9:18 AM