ARM ARM7TDMI - APB Expansion Interface

Open Access
Expanding and Monitoring the APB
5-2
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
5.1 APB Expansion Interface
Note Please refer to the AMBA Specification (ARM IHI 0001) for a detailed description of
the signals mentioned in this section.
5.1.1 Headers and pinout
The APB expansion interface comprises six 20-way box headers horizontally mounted along
the bottom edge of the development card. The headers are numbered POD1 to POD6.
Each header has a pinout that is compatible with Hewlett Packard HP1650B series logic
analyser pods (HP01650-63203). Unconnected pins are labelled NC. These pins can be
used to connect other signals to the header if required.
Note
If the logic analyser pods described are used, they supply +5V on pin 1, so this should not
be connected to any output on the board. The logic analyser pods have signal inputs on pins
4–19 and a trigger input on pin 3.
The pods are assigned as follows:
POD1: low APB data bus P_D[15:0] trigger B_CLK
POD2: high APB data bus P_D[31:16] no trigger input
POD3: low APB address bus P_A[15:0] trigger nB_CLK
POD4: high APB address bus P_A[31:16] no trigger input
POD5: APB control signals trigger P_STB
POD6: unassigned, for future expansion
Figure 5-1: Pods 1 and 2
POD1 POD2
NC 1 2 VCC NC 1 2 VCC
B_CLK 3 4 P_D[15] NC 3 4 P_D[31]
P_D[14] 5 6 P_D[13] P_D[30] 5 6 P_D[29]
P_D[12] 7 8 P_D[11] P_D[28] 7 8 P_D[27]
P_D[10] 9 10 P_D[9] P_D[26] 9 10 P_D[25]
P_D[8] 11 12 P_D[7] P_D[24] 11 12 P_D[23]
P_D[6] 13 14 P_D[5] P_D[22] 13 14 P_D[21]
P_D[4] 15 16 P_D[3] P_D[20] 15 16 P_D[19]
P_D[2] 17 18 P_D[1] P_D[18] 17 18 P_D[17]
P_D[0] 19 20 GND P_D[16] 19 20 GND
hrg.book Page 2 Wednesday, July 22, 1998 9:18 AM