ARM ARM7TDMI - APB Timing on the ARM Development Board

Open Access
Expanding and Monitoring the APB
5-6
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
5.3 APB Timing on the ARM Development Board
The AMBA specification does not specify bus timing, as this depends upon the technology
used. For expansion on the ARM Development Board it is important to have some timing
guidelines. To assist with this, the following timings have been defined:
Figure 5-4: APB timings on the ARM Development Board
This shows a read and write cycle, separated by an idle cycle. If multiple reads or writes
occur, they are not separated by an idle cycle, and this gives the minimum Tpd of 40ns at
25MHz.
5.3.1 P_STB signal
Figure 5-4: APB timings on the ARM Development Board shows that the P_STB signal
lasts for two B_CLK cycles. This is because the APB slaves are implemented in a Xilinx
FPGA, which is a relatively slow device.
If the system clock frequency is set at 20MHz or below, P_STB need only last for one
B_CLK cycle. By inserting a link the APB bridge is instructed to shorten the P_STB HIGH
pulse to one B_CLK cycle. Refer to section
3.2.8 APB and NISA Bridge on page 3-14 for
details.
To implement slower APB slaves, it is necessary to reprogram the APB bridge MACH chip
so that additional wait states are inserted. Refer to
Chapter 10, Programming the MACH
and PAL Devices
for further details of this procedure.
READ CYCLE IDLE WRITE CYCLE
TpeTpe TpdTpd
Tpss Tpsh
Tpas Tpah
Tpws Tpwh
Tpdr Tpdz Tpds Tpdh
Tpc Tpc
0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns
B_CLK
P_STB
P_SEL
P_A
P_WRITE
P_D
hrg.book Page 6 Wednesday, July 22, 1998 9:18 AM