Open Access
The Logic Analyser Interface
7-4
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
7.1.2 List of signals
The following list describes each signal.
Signal Description
D[31:0] data bus
A[31:0] APB address bus
MCLK system clock (equivalent to B_CLK)
PIPEF pipeline full
nM[4:0] processor mode
MAS[1:0] transfer size (equivalent to B_SIZE[1:0])
nRW read/write (equivalent to B_WRITE)
nMREQ memory request
nFIQ fast interrupt request
nIRQ interrupt request
nRESET processor reset (equivalent to B_RES[1])
TBIT Thumb bit
nEXEC instruction not executed
nOPC opcode fetch
SEQ sequential address
ABORT memory abort
PWAIT processor wait
ECLK external clock output
nTRANS processor user mode
TRAN[1:0] processor BC[1:0] (equivalent to B_TRAN[1:0])
CPA co-processor absent
CPB co-processor busy
nCPI co-processor instruction
VDD +3.3V
VSS system ground
Table 7-1: Logic analyser pod signals
hrg.book Page 4 Wednesday, July 22, 1998 9:18 AM
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