Open Access
The Test Interface
8-2
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
8.1 Introducing the Test Interface
The test interface comprises:
• a controller
• a number of bidirectional latched transceivers that control flow between the test
bus and ASB
The test interface is the default ASB master. This means that if no other master is requesting
the bus, the arbiter grants access to the test interface controller (TIC).
Using the test bus interface, you can gain control of the ASB in real time and perform
manufacturing test and in-circuit diagnostics. On a circuit board this is not usually a problem,
but the ARM Development Board is a board-level implementation of a typical ASIC, where it
would not be possible to examine the internal connections.
Note
Refer to the AMBA Specification (ARM IHI 0001) for details of the test port provided.
8.1.1 External signals
The following external signals are defined:
T_CLK test clock input
T_REQA test bus request A input
T_REQB test bus request B input
T_ACK test acknowledge output
T_D[31:0] test bus bi-directional
B_D[31:0] ASB data bus bi-directional
B_A[31:0] ASB address bus bi-directional
hrg.book Page 2 Wednesday, July 22, 1998 9:18 AM
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