ARM ARM7TDMI - Introduction

Open Access
Programming the APB FPGA
9-2
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
9.1 Introduction
The ARM Development Board has one Xilinx 4000 series field programmable gate array
(
FPGA ).
The FPGA is an array of
configurable logic blocks ( CLBs ) and in/out blocks ( IOBs ).
The interconnection between CLBs and IOBs, and their function is configured by
programming SRAM cells.
Programming typically occurs on power-up and takes a few milliseconds. On power-up, the
FPGA reads its mode pins (MODE[2:0]). These determine how the internal SRAM is to be
programmed.
9.1.1 APB slaves and standard peripherals
The FPGA is used to implement a number of APB slaves. These are as follows:
• interrupt controller (11 IRQ sources and one FIQ source)
• two 16-bit counter/timers with 8 bit prescalers
• reset and pause (standby) controller
This is a set of standard peripherals common to most AMBA systems. These peripherals are
mapped into the APB memory area, which is any address between 0x0A000000 and
0x0BFFFFFF.
Further information about these peripherals can be found in the
Reference Peripherals
Specification (ARM DDI 0062)
.
The base addresses shown in
Table 9-1: Base addresses have been implemented on the
board:
For a full system memory map, please refer to the
Target Development System User Guide
(ARM DUI 0061)
.
Address Name
0x0A000000 Interrupt Controller base (ICBase)
0x0A800000 Counter Timer base (CTBase)
0x0B000000 Reset and Pause Controller base (RPCBase)
0x0B800000 Expansion (spare for user functions)
Table 9-1: Base addresses
hrg.book Page 2 Wednesday, July 22, 1998 9:18 AM