ARM ARM7TDMI - Top-Level Diagram

Open Access
A-3
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.2 Top-level Diagram
Date: March 2, 1996 Sheet
Size Document Number
B ARM EOI-0011B (CHAMP
Title
ARM7T Development Board (
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
R
B
ASB SLAVES
ASBSLAVE.SCH
B_D[31..0]
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
ARMnFIQ
ARMnIRQ
REMAP
STANDBY
ARMCOMMTX
ARMCOMMRX
B_A[31..0]
B_WRITE
B_SIZE[1..0]
nB_CLK[6..0]
BIGEND
B_CLK2X[1..0]
REFCLK
NISARST
B_RES[2..0]
B_WAIT
B_LAST
COMMCLK
B_CLK[4..0]
nINTASB[1..0]
nFIQSRC
NISACLK0
REFCLK
B_RES[2..0]
B_WAIT
B_LAST
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
D_SELASB0
D_SELASB1 COMMCLK
ASB SYSTEM MODULES
SYSMODS.SCH
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
D_SELASB0
D_SELASB1
A_REQTIC
A_REQARM
A_REQ002
A_GNTTIC
A_GNTARM
A_GNT001
A_GNT002
STANDBY
REMAP
B_RES[2..0]
B_A[31..2]
B_TRAN[1..0]
nSYSRST
NISARST
A_REQ001
nENASB[1..0]
nJTRST
nB_CLK[8..7]
B_CLK5
B_CLK7
B_WAIT
B_LAST
B_ERROR
B_LOCK
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_RES[2..0]
B_PROT[1..0]
B_LOCK
B_WAIT
B_TRAN[1..0]
B_WAIT
B_LAST
B_ERROR
B_A[31..2]
nB_CLK[8..7]
B_CLK5
nENASB[1..0]
B_LOCK
ARM MASTER
MASTER.SCH
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_PROT[1..0]
B_LOCK
B_WAIT
B_LAST
B_ERROR
ARMnFIQ
ARMnIRQ
A_REQARM
A_GNTARM
A_GNT001
ARMCOMMRX
ARMCOMMTX
BIGEND
B_RES[2..0]
nSYSRST
A_REQ001
B_CLK6
nJTRST
ARMnFIQ
ARMnIRQ
A_GNTARM
A_REQARM
A_GNT001
A_REQ001
BIGEND
B_CLK6
nJTRST
TEST INTERFACE CONTROLLER
TIC.SCH
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
A_GNTTIC
B_PROT[1..0]
B_LOCK
B_WAIT
B_ERROR
B_LAST
A_REQTIC
B_CLK9
nB_CLK9
B_RES[1..0]
B_CLK9
nB_CLK9
B_LAST
B_ERROR
B_A[31..0]
B_D[31..0]
REMAP
STANDBY
A_REQTIC
A_REQARM
A_REQ001
A_REQ002
ARMCOMMRX
ARMCOMMTX
nSYSRST
nSYSRST
B_CLK7 B_RES[2..0]
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
A_GNTTIC
A_GNTARM
A_GNT001
A_GNT002
B_CLK[4..0]
nB_CLK[6..0]
B_CLK2X[1..0]NISARST
NISARST
nJTRST
NISACLK0
n
n
A
A
DISTRIBUTE TEST PINS OVER BOARD
POWER SUPPLY
POWER.SCH
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
ASB EXPANSION
ASBEXP.SCH
A_GNT001
A_GNT002
D_SELASB0
D_SELASB1
A_REQ002
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_RES[2..0]
B_PROT[1..0]
B_LOCK
B_WAIT
B_LAST
B_ERROR
nINTASB[1..0]
nFIQSRC
A_REQ001
nENASB[1..0]
B_CLK10
nB_CLK10
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
B_WRITE
B_SIZE[1..0]
B_TRAN[1..0]
B_PROT[1..0]
B_LOCK
B_WAIT
A_REQTIC
B_TRAN[1..0]
B_RES[2..0]
B_PROT[1..0]
B_LOCK
B_WAIT
B_LAST
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_LAST
B_ERROR
A_GNTTIC
B_RES[1..0]
SPARE CLOCK POINTS
OSCILLATORS
OSC.SCH
REFCLK
B_CLK2X[1..0]
nB_CLK[10..0]
COMMCLK
NISACLK[1..0]
B_CLK[10..0]
1
V1
1
V2
B_CLK2X[1..0]
B_ERROR
D_SELASB0
D_SELASB1
A_GNT001
A_GNT002
REFCLK
nB_CLK10
nB_CLK[10..0]
COMMCLK
B_CLK[10..0]
NISACLK[1..0]
B_CLK10
B_CLK8
NISACLK1
1
TP1
TESTPIN
A_REQ001
A_REQ002
nINTASB[1..0]
nFIQSRC
nENASB[1..0]
GND
BOARD OUTLINE
DRAWING.SCH
1
TP2
TESTPIN
1
TP3
TESTPIN
1
TP4
TESTPIN
1
TP5
TEST
P
GND GND GND GND
h
rg.
b
oo
k
P
age
3
W
e
d
nes
d
ay,
J
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l
y
22
,
1998
9
:
18
AM