ARM ARM7TDMI - Data Timed Signals

Open Access
A-5
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.4 Crystal Oscillator and Clock Distribution
Date: March 8, 1996 Sheet
Size Document Number
B ARM EOI-0011B (OSC.
Title
Crystal oscillator and clock
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
MONITOR POINTS
DRAM REF
R
BAUD RAT
E
1
V12
1
V13
1
V14
1
V15
1
V16
C0
C1
C2
C3
REFCLK
COMMCLK
I3
5
I4
6
I5
7
NC
8
I6
9
I7
10
I8
11
I
9
1
2
I
1
0
1
3
G
N
D
1
4
N
C
1
5
I
1
1
1
6
I
O
0
1
7
I
O
1
1
8
I02
19
IO3
20
IO4
21
NC/GND
22
IO5
23
IO6
24
IO7
25
I
O
8
2
6
I
O
9
2
7
V
C
C
2
8
N
C
1
C
L
K
/
I
0
2
I
1
3
I
2
4
U2
22V10PLCC-7
R40
10K
R41
10K
R42
10K
R43
10K
R44
10K
R45
10K
R46
10K
R47
10K
R49
10K
C
O
M
M
C
L
K
B
_
C
L
K
2
X
2
V
C
C
SEL0
SEL1
SEL2
SEL3
VCC
REFRESH CLOCK DIVIDER
distributors below
Connect to clock
CLKSEL SYSCLK
2 1 0 (MHz)
R6
10K
1
V3
1
2
3
4
8
7
6
5
S1
SW DIP-4
VCCPLL
CLKSEL0
CLKSEL2
CLKSEL1
SYSCLK
GND
REF1
POWERDN
SYSCLK2X
VCC
PLL CLOCK GENERATOR
SPECIAL LAYOUT REQUIRED
X1
14.318MHz
1.8MHZ
1
X2
2
X1/CLK
3
VCC
4
GND
5
32MHZ
6
24MHZ
7
12MHZ
8
AGND
9
OE
10
S2
11
PD
12
REF0
13
REF1
14
GND
15
VCC
16
2XCLK
17
CLK
18
S1
19
S0
20
U5
W48C55-62
R50
10K
VCCPLL
GND
AGND
CLKOE
COMMCLK
CLK24MHZ
CLK32MHZ
VCC
Fit resistors to
terminate alternate
1
2
PL1
EXTCLK
R36
47R
DO NOT FIT
1
2
PL2
EXTCLK
R38
10R
R39
10R
GNDAGND
VCCVCCPLL
EXTSCLK
EXTSCLK2X
GND
GND
---------------
0 0 0 4
0 1 0 16
0 1 1 20
1 0 0 25
1 0 1 33
1 1 0 40
1 1 1 50
0 0 1 8
NOTE: NOT DESIGNED
ABOVE 25MHz
FOR OPERATION
SPARE INPUTS
---------------
open = 1, closed = 0
PAL WILL FILTER
INVALID SELECTIONS
GND
SERIES TERMINATION RESISTORS
1
V7
1
V8
1
V9
1
V10
1
V11
G
N
D
SP4
SP5
SP6
SP7
G
N
D
SP8
SPARE I/O
1
V17
1
V18
n
B
GND
CCLK_R
CCLK_R2
nB_CLK[10..0]
CLKSEL2
CLKSEL0
CLKSEL1
B
_
nB_CLK3
nB_CLK4
nB_CLK5
nB_CLK6
nB_CLK7
nB_CLK8
nB_CLK9
B_CLK0
B_CLK1
B_CLK2
B_CLK3
B_CLK4
B_CLK5
nB_CLK10
nB_CLK0
nB_CLK1
nB_CLK2
B_CLK6
B_CLK7
B_CLK8
B_CLK9
B_CLK[10..0]
R10
33R
R11
33R
R12
33R
R13
33R
R14
33R
R15
33R
R16
33R
R17
33R
R18
33R
R19
33R
R20
33R
R21
33R
R22
33R
R23
33R
R24
33R
R25
33R
R26
33R
R27
33R
R28
33R
R29
33R
R30
33R
R31
33R
VCC
VCC
GND
nB_C5
nB_C6
nB_C7
nB_C8
nB_C9
nB_C10
nB_C0
nB_C1
nB_C2
nB_C3
nB_C4
nB_C5
nB_C6
nB_C7
nB_C8
nB_C9
nB_C10
B_C0
B_C1
B_C2
B_C3
B_C4
B_C5
GND
B_C6
B_C7
B_C8
B_C9
B_C5
B_C6
LOW-SKEW CLOCK DISTRIBUTION
VCCA
1
OA0
2
OA1
3
OA2
4
GNDA
5
OA3
6
OA4
7
GNDQ
8
OEA
9
INA
10
INB
11
OEB
12
MON
13
OB4
14
OB3
15
GNDB
16
OB2
17
OB1
18
OB0
19
VCCB
20
U3
FCT805T
VCCA
1
OA0
2
OA1
3
OA2
4
GNDA
5
OA3
6
OA4
7
GNDQ
8
OEA
9
INA
10
INB
11
OEB
12
MON
13
OB4
14
OB3
15
GNDB
16
OB2
17
OB1
18
OB0
19
VCCB
20
U4
FCT806T
1
V20
1
V21
1
V22
R32
33R
VCC
VCC
GND
GND
nB_C0
nB_C1
nB_C2
nB_C3
nB_C4
B_C0
B_C1
GNDB_C2X0
B_C2X1
B_C2X2
VCC
GND
GND
B_CLK2X2
ALTERNATIVE CLOCK INPUTS
Must disable system
clock inputs.
links below.
clock by moving
VCCA
1
OA0
2
OA1
3
OA2
4
GNDA
5
OA3
6
OA4
7
GNDQ
8
OEA
9
INA
10
INB
11
OEB
12
MON
13
OB4
14
OB3
15
GNDB
16
OB2
17
OB1
18
OB0
19
VCCB
20
U6
FCT805T
1
V23
1
V24
1
V25
R37
47R
DO NOT FIT
VCC
GND
GND
GND
N_C0
N_C1
GND
GND
Default A-C
SELECT NISA CLOCK SOURCE
Default A-C
Default A-C
A
1
C
2
B
3
LK1
SMLINK
CLK24MHZ
CLK32MHZ
NCLK
DECOUPLING CAPACITORS
DISTRIBUTE SYSTEM CLOCKS
SELECT INTERNAL OR
EXTERNAL CLOCK SOURCES
C8
2u2
C11
100n
A
1
C
2
B
3
LK2
SMLINK
A
1
C
2
B
3
LK3
SMLINK
GND
GND
B_C2
B_C3
B_C4
GND
SCLK
SYSCLK
EXTSCLK
SCLK2X
SYSCLK2X
EXTSCLK2X
VCCPLL
C6
100n
C7
100n
C9
100n
C10
100n
R33
33R
R34
33R
R35
33R
R48
33R
VCC
GND
GND
GND
B_C10B_C7
B_C8
B_C9
B_C10
N_C0
N_C1
B_C2X0
B_C2X1
VCC
GND
N
I
B
_
B_CLK10
NISACLK0
NISACLK1
B_CLK2X0
B_CLK2X1
B_CLK2X[1..0]
NISACLK[1..0]
h
rg.
b
oo
k
P
age
5
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM