ARM ARM7TDMI - ASB Slaves; A.5 ASB Slaves

Open Access
A-6
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.5 ASB Slaves
Date: February 26, 1996 Sheet
Size Document Number
B ARM EOI-0011B (ASBSLA
V
Title
ASB Slaves
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
APB AND NISA BRI
D
APBNISA.SCH
B_D[31..0]
B_RES[2..0]
B_A[31..0]
B_WRITE
B_SIZE[1..0]
D_SELNISA
D_SELAPB
ARMCOMMTX
ARMCOMMRX
B_CLK[2..0]
ARMnFIQ
ARMnIRQ
STANDBY
REMAP
B_WAIT
NISARST
COMMCLK
nB_CLK[2..1]
nFIQSRC
nINTASB[1..0]
NISACLK0
B_D[31..0]
B_WRITE
B_SIZE[1..0]
D_SELNISA
B_A[31..0]
D_SELAPB
B_RES[2..0]
COMMCLK
ONCHIP (SYNC SRAM) SLAVE
ONCHIP.SCH
B_D[31..0]
B_WAIT
B_CLK2X[1..0]
D_SELSSRAM
BIGEND
B_RES0
B_WRITE
B_SIZE[1..0]
B_A[18..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_WAIT
B_A[18..0]
B_RES0
D_SELSSRAM
B_CLK2X[1..0]
DRAM SLAVE
DRAM.SCH
M_D[31..0]
B_WAIT
B_LAST
D_SELDRAM
BIGEND
B_RES0
B_A[25..0]
B_WRITE
B_SIZE[1..0]
REFCLK
nB_CLK0
nOEMD
nOEBD
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_RES[2..0]
B_WAIT
B_LAST
B_LAST
M_D[31..0]
B_WRITE
B_SIZE[1..0]
B_WAIT
B_A[25..0]
B_RES0
B_RES[2..0]
B_WAIT
B_LAST
B_A[31..0]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
nB_CLK0
D_SELNISA
B_CLK[4..0]
nINTASB[1..0]
nB_CLK[6..0]
D_SELROM
D_SELAPB
D_SELSSRAM
D_SELSRAM
D_SELDRAM
B_CLK2X[1..0]
BIGEND
D_SELDRAM
nOEMD
nOEBD
B_A[17..2]
B_D[31..0]
D_SELSSRAM
D_SELSRAM
D_SELDRAM
D_SELROM
D_SELAPB
D_SELNISA
nINTASB[1..0]
B_CLK[4..0]
nB_CLK[6..0] REFCLK
nB_CLK6
B_CLK2X[1..0]
ADDRESS AND DATA BUFFERS
MEMBUF.SCH
B_D[31..0]
M_A[17..2]
B_A[17..2]
M_D[31..0]
nB_CLK6
nOEMD
nOEBD
nOEMD
nOEBD
M_D[31..0]
M_A[17..2]
SIGNALS DRIVEN BY SRAM AND
DRAM CONTROLLERS
R51
1K
R52
1K
BIGEND
nOEMD nOEBD
VCC VCC
B_WAIT
nFIQSRC
nINTASB[1..0]
ARMCOMMTX
ARMCOMMRX
B_CLK[2..0]
nB_CLK[2..1]
ARMnFIQ
ARMnIRQ
STANDBY
NISARST
NISACLK0
1
2
LK4
LINK
R53
10K
1
2
U24A
74HCT14
REMAP
BIGEND
VCC
GND
EPROM/FLASH SLAVE
EPROM.SCH
B_D[31..0]
B_WAIT
B_RES0
B_WRITE
B_SIZE[1..0]
M_A[17..2]
D_SELROM
B_A[1..0]
B_A18
B_CLK4
nB_CLK[5..4]
B_D[31..0]
B_WRITE
B_SIZE[1..0]
B_WAIT
M_A[17..2]
B_RES0
SRAM SLAVE
SRAM.SCH
B_WRITE
B_SIZE[1..0]
M_A[17..2]
M_D[31..0]
B_RES0
B_WAIT
D_SELSRAM
B_A[1..0]
B_A18
BANKSEL
BIGEND
B_CLK3
nB_CLK3
nOEMD
nOEBD
nFIQSRC
ARMCOMMRX
ARMCOMMTX
REFCLK
ARMnFIQ
ARMnIRQ
REMAP
STANDBY
NISARST
COMMCLK
NISACLK0
M_D[31..0]
B_WRITE
B_SIZE[1..0]
B_WAIT
B_RES0
M_A[17..2]
REMAP
STANDBY
ARMnFIQ
ARMnIRQ
nFIQSRC
ARMCOMMRX
ARMCOMMTX
REFCLK
NISARST
COMMCLK
NISACLK0
BANKSEL PARTITIONS SRAM
INTO TWO LOGICAL BANKS
OF 256K BYTES EACH
BIGEND
D_SELSRAM
B_A18
B_A[1..0]
nB_CLK3
B_A18
B_CLK3
nOEMD
nOEBD
nB_CLK[5..4]
D_SELROM
B_A18
B_A[1..0]
B_CLK4
OUT - little endian (default)
IN - big endian
SELECT BIG OR LITTLE ENDIAN
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