ARM ARM7TDMI - EPROM;FLASH ASB Slave

Open Access
A-8
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.7 EPROM/FLASH ASB Slave
Date: February 26, 1996 Sheet
Size Document Number
B EOI-0011B (EPROM.S
Title
EPROM/FLASH ASB Sl
a
CB1 4JN
CAMBRIDGE
CHERRY HINTON
FULBOURN ROAD
(C) ADVANCED RISC MAC
8-BIT EPROM/FLASH
A18
1
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D0
13
D1
14
D2
15
GND
16
D3
17
D4
18
D5
19
D6
20
D7
21
CE
22
A10
23
OE
24
A11
25
A9
26
A8
27
A13
28
A14
29
A17
30
WE
31
VCC
32
U12
AT29C512/010/020/040
VCC
nWE
nOE
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15
M_A16
M_A17
M_A18
M_D4
M_D5
GND
G
N
D
V
C
C
O
U
T
M
D
M
_
D
0
M
_
D
1
M
_
D
2
M
_
D
3
M
_
D
8
M
_
D
9
M
_
D
1
0
M
_
D
1
1
SET LINKS TO SELE
C
8 OR 16-BIT DEVI
C
DATA PATH ROUTER
IO8
12
IO9
13
IO10
14
IO11
15
IO12
16
IO13
17
IO14
18
IO15
19
CLK0/I0
20
VCC
21
GND
22
CLK1/I1
23
IO16
24
IO17
25
IO18
26
IO19
27
IO20
28
IO21
29
IO22
30
IO23
31
GND
32
I
O
2
4
3
3
I
O
2
5
3
4
I
O
2
6
3
5
I
O
2
7
3
6
I
O
2
8
3
7
I
O
2
9
3
8
I
O
3
0
3
9
I
O
3
1
4
0
I
2
4
1
V
C
C
4
2
G
N
D
4
3
V
C
C
4
4
I
O
3
2
4
5
I
O
3
3
4
6
I
O
3
4
4
7
I
O
3
5
4
8
I
O
3
6
4
9
I
O
3
7
5
0
I
O
3
8
5
1
I
O
3
9
5
2
G
N
D
5
3
IO40
54
IO41
55
IO42
56
IO43
57
IO44
58
IO45
59
IO46
60
IO47
61
CLK2/I3
62
VCC
63
GND
64
CLK3/I4
65
IO48
66
IO49
67
IO50
68
IO51
69
IO52
70
IO53
71
IO54
72
IO55
73
GND
74
I
O
5
6
7
5
I
O
5
7
7
6
I
O
5
8
7
7
I
O
5
9
7
8
I
O
6
0
7
9
I
O
6
1
8
0
I
O
6
2
8
1
I
O
6
3
8
2
I
5
8
3
V
C
C
8
4
G
N
D
1
V
C
C
2
I
O
0
3
I
O
1
4
I
O
2
5
I
O
3
6
I
O
4
7
I
O
5
8
I
O
6
9
I
O
7
1
0
G
N
D
1
1
U11
MACH230-10
R60
10K
R61
10K
B_WAIT
B_D8
B_D9
B_D10
B
_
D
0
B
_
D
1
B
_
D
2
B
_
D
3
B
_
D
4
B
_
D
5
B
_
D
6
B
_
D
7
G
N
D
V
C
C
B_WAIT
VCCVCC
B_D[31..0]
B_RES0
B_SIZE[1..0]
B_WRITE
nB_CLK[5..4]
D_SELROM
M_A[17..2]
B_A[1..0]
B_A18
B_CLK4
B_D[31..0]
B_RES0
B_SIZE[1..0]
B_WRITE
nB_CLK[5..4]
D_SELROM
M_A[17..2]
B_A[1..0]
B_A18
B_CLK4
EPROM/FLASH CONTROLLER
SPARE INPUTS
1
V48
1
V49
B
_
S
I
Z
E
1
B
_
A
0
B
_
A
1
G
N
D
V
C
C
S
E
L
0
S
E
L
1
H
O
L
D
0
H
O
L
D
1
B
_
A
1
8
D
_
S
E
L
R
O
M
B_D11
B_D12
B_D13
B_D14
B_D15
B_D16
B_D17
B_D18
B_D19
B_D20
B_D21
B_D22
B_D23
GND
GND
VCC
SPARE I/O
1
V41
1
V42
1
V43
1
V44
1
V45
1
V46
1
V47
M_D6
M_D7
M_D12
M_D13
M_D14
M_D15
GND
VCC
B_RES0
SEL8BIT
nB_CLK5
16-BIT EPROM/FLASH
D12
7
D11
8
D10
9
D9
10
D8
11
GND
12
NC
13
D7
14
D6
15
D5
16
D4
17
D
3
1
8
D
2
1
9
D
1
2
0
D
0
2
1
O
E
2
2
N
C
2
3
A
0
2
4
A
1
2
5
A
2
2
6
A
3
2
7
A
4
2
8
A5
29
A6
30
A7
31
A8
32
NC
33
GND
34
A9
35
A10
36
A11
37
A12
38
A13
39
A
1
4
4
0
A
1
5
4
1
A
1
6
4
2
W
E
4
3
V
C
C
4
4
N
C
1
A
1
7
2
C
E
3
D
1
5
4
D
1
4
5
D
1
3
6
U1
A
T
GND
M_A0
M_A1
M_D0
M_D1
M_D2
M_D3
M_D4
M_D5
M_D6
M_D7
M
_
A
1
5
M
_
A
1
6
M
_
A
1
7
M
_
A
1
8
M
_
D
1
3
M
_
D
1
4
M
_
D
1
5
n
W
E
V
C
C
nCS8
n
C
S
1
6
n
O
E
M
_
A
1
M
_
A
2
M
_
A
3
M
_
A
4
M
_
A
5
M
_
D
0
M
_
D
1
M
_
D
2
M
_
D
3
G
N
D
V
C
C
S
E
L
0
S
E
L
1
H
O
L
D
0
H
O
L
D
1
H
O
L
D
2
T
R
A
N
S
0
T
R
A
N
S
1
T
R
A
N
S
2
GND
M_D4
M_D5
M_D6
M_D7
M_D8
M_D9
M_D10
M_D11
M_D12
G
N
D
SPARE I/O
1
V50
R62
10K
R63
10K
R64
10K
R65
10K
HOLD2
TRANS0
TRANS1
TRANS2
GND
EPROM
SEL8BIT
B
_
D
2
4
B
_
D
2
5
B
_
D
2
6
B
_
D
2
7
B
_
D
2
8
B
_
D
2
9
B
_
D
3
0
B
_
D
3
1
O
U
T
B
D
V
C
C
M_A18
nB_CLK4
nCS16
VCC
CYCLE COUNTER
IO5
7
IO6
8
IO7
9
I0
10
I1
11
GND
12
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
I
O
1
2
1
8
I
O
1
3
1
9
I
O
1
4
2
0
I
O
1
5
2
1
V
C
C
2
2
G
N
D
2
3
I
O
1
6
2
4
I
O
1
7
2
5
I
O
1
8
2
6
I
O
1
9
2
7
I
O
2
0
2
8
IO21
29
IO22
30
IO23
31
I3
32
I4
33
GND
34
CLK1/I5
35
IO24
36
IO25
37
IO26
38
IO27
39
I
O
2
8
4
0
I
O
2
9
4
1
I
O
3
0
4
2
I
O
3
1
4
3
V
C
C
4
4
G
N
D
1
I
O
0
2
I
O
1
3
I
O
2
4
I
O
3
5
I
O
4
6
U10
MACH210A-7
1
V35
1
V36
B_WAIT
B_WRITE
B_SIZE0
CYC1
CYC0
GND
OUTBD
OUTMD
CCNT0
CCNT1
B_CLK4
DECOUPLING CAPACITORS
MONITOR POINTS
TICK COUNTER
C18
10u
C19
100n
C20
100n
C21
100n
C22
100n
C23
100n
1
V37
1
V38
1
V39
T
C
N
T
0
T
C
N
T
1
T
C
N
T
2
V
C
C
G
N
D
n
O
E
n
W
E
M
_
A
0
M
_
A
1
B
_
R
E
S
0
n
C
S
8
C24
100n
C25
100n
C26
100n
+
1
+
3
+
5
+
7
+
2
+
4
+
6
+
8
LK6
LINK-4
VCC
GND
GND
VCC
GND
open = EPROM, closed = FLASH
open = 8 bit, closed = 16-bit
00 2
CYC No. of cycles
10 4
01 3
11 5
cycle information, see below
EPROM
SEL8BIT
CYC1
CYC0
WHEN EPROM IS SELECTED
WE IS CONNECTED TO A18
h
rg.
b
oo
k
P
age
8
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM