ARM ARM7TDMI - SRAM ASB Slave

Open Access
A-10
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
Board Schematics
A.9 SRAM ASB Slave
Date: February 26, 1996 Sheet
Size Document Number
B ARM EOI-0011B (SRAM
.
Title
SRAM ASB Slave
CB1 4JN
Cambridge
Cherry Hinton
Fulbourn Road
(c) ADVANCED RISC MACHI
N
R96
10K
VCC
FAST SRAM BANK
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D0
13
D1
14
D2
15
GND
16
D3
17
D4
18
D5
19
D6
20
D7
21
CE1
22
A10
23
OE
24
A11
25
A9
26
A8
27
A13
28
WE
29
CE2
30
A15
31
VCC
32
U15
SRAM128K8-20
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15
M_A16
M_A17M_A18
nCS
VCC
nOE
nWE3
M_D24
M_D25
M_D26 M_D28
M_D29
M_D30
M_D31
B_WAIT
nOEMD
nOEBD
n
W
E
1
n
W
E
2
n
W
E
3
V
C
C
G
N
D
B
A
N
K
S
E
L
n
W
E
0
SRAM CONTROLLER
M_A[17..2]
M_D[31..0]
B_A[1..0]
B_A18
B_SIZE[1..0]
B_WRITE
B_RES0
D_SELSRAM
nB_CLK3
B_CLK3
B
_
W
A
I
T
B
_
W
R
I
T
E
B
_
S
I
Z
E
0
B
_
A
1
8
M_A[17..2]
M_D[31..0]
B_A[1..0]
B_SIZE[1..0]
B_WRITE
B_RES0
D_SELSRAM
B_WAIT
nOEMD
nOEBD
B_CLK3
nB_CLK3
B_A18
IO5
7
IO6
8
IO7
9
I0
10
I1
11
GND
12
CLK0/I2
13
IO8
14
IO9
15
IO10
16
IO11
17
I
O
1
2
1
8
I
O
1
3
1
9
I
O
1
4
2
0
I
O
1
5
2
1
V
C
C
2
2
G
N
D
2
3
I
O
1
6
2
4
I
O
1
7
2
5
I
O
1
8
2
6
I
O
1
9
2
7
I
O
2
0
2
8
IO21
29
IO22
30
IO23
31
I3
32
I4
33
GND
34
CLK1/I5
35
IO24
36
IO25
37
IO26
38
IO27
39
I
O
2
8
4
0
I
O
2
9
4
1
I
O
3
0
4
2
I
O
3
1
4
3
V
C
C
4
4
G
N
D
1
I
O
0
2
I
O
1
3
I
O
2
4
I
O
3
5
I
O
4
6
U16
MACH210A-7
1
V63
1
V64
BANKSEL
BIGEND
B_SIZE1
B_A0
B_A1
B_RES0
GND
nOEBD
nOEMD
D_SELSRAM
BANKSEL
BIGEND
B_CLK3
CCNT0
CCNT1
SPARE I/O
R100
10K
1
V61
1
V62
1
V65
1
V66
1
V67
1
V68
nCS
GND
M_A18
BIGEND
nB_CLK3
TCNT2
TCNT1
nOE
VCC
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D0
13
D1
14
D2
15
GND
16
D3
17
D4
18
D5
19
D6
20
D7
21
CE1
22
A10
23
OE
24
A11
25
A9
26
A8
27
A13
28
WE
29
CE2
30
A15
31
VCC
32
U17
SRAM128K8-20
GND
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15
M_A16
M_A17M_A18
nCS
GND
VCC
nOE
nWE2
M_D16
M_D17
M_D18
M_D19
M_D20
M_D21
M_D22
M_D23
M_D27
R97
10K
VCC
R98
10K
VCC
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D0
13
D1
14
D2
15
GND
16
D3
17
D4
18
D5
19
D6
20
D7
21
CE1
22
A10
23
OE
24
A11
25
A9
26
A8
27
A13
28
WE
29
CE2
30
A15
31
VCC
32
U18
SRAM128K8-20
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
D0
13
D1
14
D2
15
GND
16
D3
17
D4
18
D5
19
D6
20
D7
21
CE1
22
A10
23
OE
24
A11
25
A9
26
A8
27
A13
28
WE
29
CE2
30
A15
31
VCC
32
U19
SRAM128K8-20
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15
M_A16
M_A17M_A18
nCS
GND
VCC
nOE
nWE1
M_D8
M_D9
M_D10
M_D11
M_D12
M_D13
M_D14
M_D15
00 2
CYC No. of cycles
10 4
01 3
11 5
MONITOR POINTS
B
1
C
Y
C
0
B
1
C
Y
C
1
B
1
S
I
Z
0
B
1
S
I
Z
1
G
N
D
V
C
C
T
C
N
T
0
BANK0
MONITOR POINTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S2
SW DIP-8
R101
10K
R102
10K
R103
10K
R104
10K
R105
10K
R106
10K
R107
10K
R108
10K
B0CYC0
B0CYC1
B0SIZ0
B0SIZ1
B
0
C
Y
C
0
B
0
C
Y
C
1
B
0
S
I
Z
0
B
0
S
I
Z
1
VCC
SELECT CYCLES AND WIDTH OF BANK
BANK 1
OPEN = 1, CLOSED = 0
C46
10u
C47
100n
C48
100n
C49
100n
C50
100n
C51
100n
B1CYC0
B1CYC1
B1SIZ0
B1SIZ1
GND
SIZ Width of bank
00 8 bit
01 16 bit
10 32 bit
11 reserved
C52
100n
VCC
GND
VCC
GND
M_A2
M_A3
M_A4
M_A5
M_A6
M_A7
M_A8
M_A9
M_A10
M_A11
M_A12
M_A13
M_A14
M_A15
M_A16
M_A17M_A18
nCS
GND
VCC
nOE
nWE0
M_D0
M_D1
M_D2
M_D3
M_D4
M_D5
M_D6
M_D7
R99
10K
VCC
h
rg.
b
oo
k
P
age
10
W
e
d
nes
d
ay,
J
u
l
y
22
,
1998
9
:
18
AM