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English
H510M-IT X/ac
e number of clocks from a Refresh command until the rst Activate command to
the same rank.
RAS to RAS Delay (tRRD_L)
e number of clocks between two rows activated in dierent banks of the same
rank.
RAS to RAS Delay (tRRD_S)
e number of clocks between two rows activated in dierent banks of the same
rank.
Write to Read Delay (tWTR_L)
e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
e number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
e number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
e time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Congure CAS Write Latency.
Third Timing
tREFI
Congure refresh cycles at an average periodic interval.
tCKE
Congure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
Turn Around Timing
Turn Around Timing Optimization
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