120
[2] MODE1 (QuadLink) (screen vertically split into 4)
The screen is split vertically into for parts and allocated from the left in the sequence of channel 1, channel 3,
channel 2 and channel 4.
Given here as an example of the resolution is 4096 × 2048, the dot clock frequency is 592 MHz with the 10bits
output.
・・・
CLK
148MHz
1CH
2CH
3CH
4CH
D 1020 D 1021 D 1022 D 1023
[9:0] [9:0] [9:0] [9:0]
D 0
[9:0]
D 1 D 2 D 3
・・・
[9:0] [9:0] [9:0]
D 2044
[9:0]
D 2045 D 2046 D 2047
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 1024 D 1025 D 1026 D 1027
D 4092
[9:0]
D 4093 D 4094 D 4095
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 3072 D 3073 D 3074 D 3075
D 3068
[9:0]
D 3069 D 3070 D 3071
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 2048 D 2049 D 2050 D 2051
1CH 2CH 3CH 4CH