Chapter 4 INTERFACE SETTINGS
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[8] MODE7 (16Lane) (vertically split into 2 + Split (1) ) (Dividing Normal Mode)
The screen is vertically divided into 2 and is output according to [Pixel Assignment of each Lane] from
each output board, then it is vertically split into 2 by 2 boards.
This example is a case where the resolution is 4096 × 2048, the dot clock frequency is 1184 MHz and the
output bit depth is 10 bits.
[Assignment of each Lane]
Lane 1-4 Lane 9-12Lane 5-8 Lane 13-16