Asus A6J - Calistoga Strapping

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LOW = Mobile Prescott
HIGH = DMI X 4 (Default)
CFG19 : DMI LANE REVERSAL
CFG16 : FSB DYNAMIC ODT
CFG7 : CPU STRAP
HIGH = Dynamic ODT Enabled (Default)
LOW = Dynamic ODT Disabled
HIGH = 1.5V
LOW = NORMAL
LOW = REVERSE LANE (Default)
LOW = RESERVED
LOW = REVERSAL
CFG[17..3] have internal pullup resistors.
CFG[20..18] have internal pulldown resistors.
SDVOCRTL_DATA has internal pulldown
resistors.
HIGH = NORMAL OPERATION
CFG11 : PSB 4X CLK ENABLE
CFG9 : PCIE GRAPHIC LANE
CFG18 : GMCH Core Voltage Level
HIGH = Dothan CPU (Default)
HIGH = LANES REVERSED
HIGH = MOBILITY
HIGH =Calistoga(Default)
LOW = DMI X 2
LOW = 1.05V (Default)
CFG10: HOST PLL VCO SELECT
CFG5 : DMI STRAP
HIGH = NORMAL OPERATION
LOW = ICH RESET DISABLE
CFG15 :ICH RESET DISABLE
Custom
11 63Tuesday, November 22, 2005
ASUSTeK COMPUTER INC
Calistoga Strapping
2.0
A6J
Charles Lee
<Variant Name>
Size Project Name
Rev
Date: Sheet
of
Title :
Engineer:
GND
GND
GND
GND
GND
+3VS
+3VS
GND
GND
GND
GND
R1104
2.2KOhm
r0402
@
1 2
R1110
2.2KOhm
r0402
@
1 2
R1101
1KOhm
@
1 2
R1106
2.2KOhm
r0402
@
1 2
R1111
2.2KOhm
r0402
@
1 2
R1103
2.2KOhm
r0402
@
1 2
R1105
2.2KOhm
r0402
1 2
R1108
2.2KOhm
r0402
@
1 2
R1102
1KOhm
@
1 2
R1107
2.2KOhm
r0402
@
1 2
R1109
1KOhm
@
1 2
MCH_CFG_77
MCH_CFG_97
MCH_CFG_187
MCH_CFG_117
MCH_CFG_167
MCH_CFG_107
MCH_CFG_57
MCH_CFG_197
MCH_CFG_157
MCH_CFG_127 MCH_CFG_137