2-20 Chapter 2: BIOS setup
2.4.3 Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press <Enter> to display the sub-menu.
Advanced Chipset Settings
WARNING: Setting wrong values in below sections
may cause the system to malfunction.
Configure DRAM Timing by SPD [Enabled]
Performance Acceleration Mode [Auto]
DRAM Idle Timer [Auto]
DRAM Refresh Rate [Auto]
Graphic Adapter Priority [VGA/Int-VGA]
Graphics Aperture Size [64MB]
MPS Revision [1.4]
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled.
Configuration options: [Disabled] [Enabled]
DRAM CAS# Latency [2.5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [2.0 Clocks] [2.5 Clocks] [3.0 Clocks]
Ajacent Cache Line Prefetch [Enabled]
Allows you to enable/disable the Ajacent Cache Line Prefetch function.
Configuration options: [Disabled] [Enabled]
CPU Internal Thermal Control [Auto]
Disables or sets the CPU internal thermal control.
Configuration options: [Disabled] [Auto]
Hyper-Threading Technology [Enabled]
Allows you to enable or disable the processor Hyper-Threading Technology.
Configuration options: [Disabled] [Enabled]
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