Asus P8Z77-I DELUXE - Page 77

ASUS P8Z77-I DELUXE
3-11
Chapter 3
tRR (DR) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRRSR [Auto]
Conguration options: [Auto] [4 DRAM Clock] – [7 DRAM Clock]
tWW (DD) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tWW (DR) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tWWSR [Auto]
Conguration options: [Auto] [4 DRAM Clock] – [7 DRAM Clock]
MISC
MRC Fst Boot [Enabled]
Conguration options: [Enabled] [Disabled]
DRAM CLK Period [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [14 DRAM Clock]
Transmitter Slew (CHA) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
Transmitter Slew (CHB) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
Receiver Slew (CHA) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
Receiver Slew (CHB) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
MCH Duty Sense (CHA) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [31 DRAM Clock]
MCH Duty Sense (CHB) [Auto]
Conguration options: [Auto] [1 DRAM Clock] – [31 DRAM Clock]
Channel A DIMM Control [Enable Both DIMMS]
Conguration options: [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1]
[Disable Both DIMMS]
Channel B DIMM Control [Enable Both DIMMS]
Conguration options: [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1]
[Disable Both DIMMS]
DRAM Read Additional Swizzle [Auto]
Conguration options: [Auto] [Enabled] [Disabled]
DRAM Write Additional Swizzle [Auto]
Conguration options: [Auto] [Enabled] [Disabled]